SystemVerilog

Professor: Sci.D., Professor

Vazgen Melikyan

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Lecture - 4
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OOP classes

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Class
 Class encapsulate class BusTran;
 Variables bit [31:0] addr, crc, data[8];
 Methods
function void display;
 Class can be $display("BusTran: %h", addr);
endfunction : display
defined in
 Program block function void calc_crc;
crc = addr ^ data.xor;
 Module block endfunction : calc_crc
 Package endclass : BusTran

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 Class(2)
class myPacket;
bit [2:0] header;
 function new () - constructor bit encode;
 This – refer to this class bit [2:0] mode;
 Function new has default bit [7:0] data;
values bit stop;

function new (bit [2:0] header = 3'h1,

bit [2:0] mode = 5); this.header =
header; this.encode = 0;
this.mode = mode;
this.stop = 1; endfunction
function display ();
$display (this.header, this.encode,
this.mode, this.stop);
endfunction
endclass
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Module and class differences

Module Class
static dynamic
instance object
Object can created and
-
detroyed
- compared
- Copied
- Inherited and changed

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 Constructing object

program automatic;
myPacket p1=new();
myPacket p2;

initial begin
p2.encode=1’b0; // runtime Error
end
class myPacket;
bit [2:0] header;
endprogram
bit encode;
bit [2:0] mode;
bit [7:0] data;
bit stop;
endclass
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Constructing object (2)
class myPacket;
bit [2:0] header;
bit encode;
bit [2:0] mode;
bit [7:0] data;
bit stop;

function new (bit [2:0] header = 3'h1,

bit [2:0] mode = 5);
// function body skiped
endfunction
endclass
initial
myPacket p1;
p1.new(1,1); // Compilation error
// myPacket p1=new(1,1);
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This keyword

class Packet;
bit [31:0] addr;

function new (bit [31:0] addr);

this.addr = addr;

endfunction

endclass

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 Local class ABC;
 is available only to the byte public_var;
methods of the same local byte local_var;
class function void display();
 is not accessible by child $display (public_var, local_var);
classes endfunction endclass
 nonlocal methods that module tb;
access local members initial begin ABC abc = new();
can be inherited and abc.display();
overridden by child class abc.public_var = 1;
abc.local_var = 1; //compilation error
end
endmodule

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Static
class Packet;
bit [15:0] addr;
bit [7:0] data;

function new (bit [15:0] ad, bit

[7:0] d); addr = ad; data = d;
$display (addr, data);
endfunction
endclass

module tb;
initial
begin Packet p1, p2, p3;
p1 = new (16'hdead, 8'h12);
p2 = new (16'hface, 8'hab);
p3 = new (16'hcafe, 8'hfc);
end endmodule
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Randomization

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randomize test

 Complex designs are better verified by

randomized tests
 Take much less effort and time

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Constraints

 Constraints use to generate random values

that satisfy all conditions

class Pkt;
rand bit [7:0] addr;
rand bit [7:0] data;

constraint addr_limit { addr <= 8'hB; }

endclass

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 rand class Packet;
rand bit [2:0] data; endclass
Can be used on
Normal variables module tb;
Arrays
initial begin
Dynamic arrays
Packet pkt = new ();
Queues for (int i = 0 ; i < 10; i++) begin
run -all; pkt.randomize ();
# KERNEL: itr=0 data=0x7 $display ("itr=%0d data=0x%0h", i,
# KERNEL: itr=1 data=0x2 pkt.data);
# KERNEL: itr=2 data=0x2
# KERNEL: itr=3 data=0x1 end
# KERNEL: itr=4 data=0x2 end
# KERNEL: itr=5 data=0x4 endmodule
# KERNEL: itr=6 data=0x0
# KERNEL: itr=7 data=0x1
# KERNEL: itr=8 data=0x5
# KERNEL: itr=9 data=0x0
# KERNEL: Simulation has finished. There
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randc
class Packet;
Can be used on randc bit [2:0] data;
Normal variables endclass
Arrays
module tb;
initial begin
Dynamic arrays Packet pkt = new ();
Queues for (int i = 0 ; i < 10; i++) begin
run -all; pkt.randomize ();
# KERNEL: itr=0 data=0x6 $display ("itr=%0d data=0x%0h", i,
# KERNEL: itr=1 data=0x3 pkt.data);
# KERNEL: itr=2 data=0x4
# KERNEL: itr=3 data=0x7 end
# KERNEL: itr=4 data=0x0 end
# KERNEL: itr=5 data=0x1 endmodule
# KERNEL: itr=6 data=0x5
# KERNEL: itr=7 data=0x2
# KERNEL: itr=8 data=0x5 // Start of a
new sequence # KERNEL: itr=9 data=0x0 #
KERNEL: Simulation has finished. There
are no more test vectors to simulate.
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 Constraint block

constraint valid_addr
{ addr [1:0] == 2'b0; addr <= 32'hfaceface; addr >= 32'hf0000000; }
constraint fast_burst
{ burst >= 3; len >= 64; size >= 128; }
constraint valid_addr {...}//Error-valid_addr already declared
constraint valid { addr >= 32'hfaceffff; } // Runtime error - solver
fails due to conflict on addr

constraint valid2 { addr <= 32'hf4000000; } // valid

constraint c_empty; // An empty constraint - does not affect

randomization

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Constraint example
class ABC;
rand bit [3:0] mode;
constraint c_mode { mode > 2; mode <= 6; };
endclass

module tb; ABC abc;

initial begin
abc = new();

for (int i = 0; i < 5; i++)begin

abc.randomize();
$display ("mode = 0x%0h", abc.mode);
end
end
endmodule

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External Constraint Example
class ABC;
rand bit [3:0] mode;

constraint c_implicit;
extern constraint c_explicit;
endclass

constraint ABC::c_implicit { mode > 2; };

constraint ABC::c_explicit { mode <= 6; };

module tb; ABC abc; initial begin

abc = new();
for (int i = 0; i < 5; i++) begin
abc.randomize();
$display ("mode = 0x%0h", abc.mode);
end
end
endmodule

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Static arrays randomization
class Packet;
rand bit [3:0] s_array [7];
endclass

module tb; Packet pkt;

initial begin pkt = new();

pkt.randomize();
$display(“static = %p", pkt.s_array);
end

endmodule

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Dynamic arrays randomization
class Packet;
rand bit [3:0] d_array [];
constraint c_array { d_array.size() > 5;
d_array.size() < 10; }
constraint c_val { foreach (d_array[i]) d_array[i] == i; }

function void display();

foreach (d_array[i])
$display ("d_array[%0d] = 0x%0h", i, d_array[i]);
endfunction
ncsim> run
endclass d_array[0] = 0x0
d_array[1] = 0x1
module tb; Packet pkt; d_array[2] = 0x2
initial d_array[3] = 0x3
begin pkt = new(); d_array[4] = 0x4
pkt.randomize(); d_array[5] = 0x5
pkt.display(); d_array[6] = 0x6
end d_array[7] = 0x7
endmodule d_array[8] = 0x8
ncsim: *W,RNQUIE: Simulation is complete.
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Queue randomization
class Packet;
rand bit [3:0] queue [$];

constraint c_array { queue.size() == 4; } endclass

module tb; Packet pkt;

initial begin
pkt = new();
pkt.randomize();
$display("queue = %p", pkt.queue);
end
endmodule

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Constraint, Expressions
class MyClass;
rand bit [7:0] min, typ,max;

constraint my_range { 0 < min;

typ < max;
typ > min;
max < 128; }

constraint my_min { min == 16; }//set min 16, rand all

constraint my_max { max >= 64; }

endclass

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Constraint, Expressions (2)

// invalid,can be one relational operator in an expression

constraint my_error { 0 < min < typ < max < 128; }

constraint my_min { min == temp.low * 9/5 + 32; }

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Inside
constraint my_range { typ > 32; typ < 256; }

constraint new_range { typ inside {[32:256]}; }

constraint spec_range { type inside {32, 64, 128}; }

Get any value outside of specified range

rand bit [2:0] typ;

constraint inv_range { ! (typ inside {[3:6]}); }

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 Weighted distributions
:= operator
rand bit [2:0] typ;

constraint dist1 { typ dist { 0:=20,

[1:5]:=50,
6:=40,
7:=10}; }

:/ operator
rand bit [2:0] typ;
constraint dist2 { typ dist { 0:/20,
[1:5]:/50,
6:/10,
7:/20}; }
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 Bidirectional constraints
class myClass;
rand bit [3:0] val; run -all;
constraint c1 { val > 3; val < 12; } # KERNEL: itr=0 typ=11
constraint c2 {val >= 10; } endclass
# KERNEL: itr=1 typ=11
module tb;
# KERNEL: itr=2 typ=11
initial begin # KERNEL: itr=3 typ=10
for (int i = 0; i < 10; i++) begin # KERNEL: itr=4 typ=11
myClass cls = new (); cls.randomize(); # KERNEL: itr=5 typ=10
$display ("itr=%0d typ=%0d", i, cls.val); # KERNEL: itr=6 typ=10
# KERNEL: itr=7 typ=10
end # KERNEL: itr=8 typ=10
end
# KERNEL: itr=9 typ=10
endmodule

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 Without solve - before
class ABC; 5 combination
rand bit a;
rand bit [1:0] b; Probability for each is 1/5
constraint c_ab { a -> b == 3'h3; }
endclass ncsim> run
a=0 b=0
module tb; a=0 b=1
initial begin a=0 b=0
ABC abc = new; a=0 b=1
for (int i = 0; i < 8; i++) a=0 b=2
begin a=1 b=3
abc.randomize(); a=0 b=3
$display( abc.a, abc.b); a=0 b=3
end
end
endmodule
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 With solve - before
class ABC;
rand bit a; Probability of a and b are
rand bit [1:0] b; same, 50%
Constraint c_ab { a -> b == 3'h3;
solve a before b; } endclass
ncsim>
run
module tb;
a=1 b=3
a=1 b=3
initial begin
a=0 b=1
ABC abc = new;
a=0 b=0
for (int i = 0; i < 8; i++)
a=0 b=0
begin
a=0 b=1
abc.randomize();
a=1 b=3
$display (abc.a, abc.b);
a=0 b=2
end
end
endmodule
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Soft constraint
ncsim> run
constraint c_data { soft data >= 4; abc = 0x4
data <= 12; } abc = 0x8
… abc = 0x4
abc.randomize(); abc = 0x7
… abc = 0x7
abc.randomize() with { data == 2; };
…

ncsim: *W,RNDOCS: These variables contribute to

the set of conflicting constraints:
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Static constraint

 Static - constraint_mode() method turn off

constraints for all instance
 Non-static – turn off for one instance
…
static constraint c2 { a < 12; }
class [class_name];
…
...
initial begin
static
ABC obj1 = new;
constraint[constraint_name]
[definition] ABC obj2 = new;
endclass
obj1.c1.constraint_mode(0);
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Disable Constraints
// Called as a task
class_obj.const_name.constraint_mode(0); // Turn off

class_obj.const_name.constraint_mode(1); // Turn on

// Called as a function
status = class_obj.const_name.constraint_mode(); // return
status

module tb;
initial begin
Fruits f = new ();
$display (f.num);
f.c_num.constraint_mode(0);
if (f.c_num.constraint_mode ())
$display ("Constraint c_num is enabled");
else $display ("Constraint c_num is disabled");
f.randomize ();
$display ("After randomization num = %0d", f.num);
end
endmodule
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Disable randomization
[class_object].[variable_name].rand_mode (0);

[class_object].[variable_name].rand_mode (1);

pkt1.b.rand_mode (0);
pkt1.b.rand_mode (1);

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Example

module half_adder(
input x, y, enable,
output carry, result);

assign carry=enable?x&y:0;
assign result=enable?x^y:0;

endmodule half_adder;

x
Half carry
y
Adder result
enable

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Example
module test;

class Packet;
rand logic x,y,enable;
endclass;

Packet pkt = new ();

logic x,y,enable;
wire carry,result;

half_adder half_adder_tb(x,y,enable,carry,result);
initial begin
for (int i = 0 ; i < 10; i++) begin
pkt.randomize ();
x=pkt.x; y=pkt.y;
enable=pkt.enable;
$display("x=",pkt.x," y=",pkt.y," enable=",pkt.enable);
#5;
$display("result=",result," carry=",carry,"\n");
end
end
endmodule
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