9/30/25, 6:05 PM C.

RISC-V CPU Design - Mazesolver Bot 🌳

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Task 1C: RISC-V CPU

Problem Statement
To implement the RISC-V CPU in Verilog for rv32i ISA.

Guide: This is one of the important tasks, Go through all the resources provided in the
RISC-V CPU 🔗 learn section to help yourselves.

 
Description
In this task, teams need to complete the RISC-V CPU from the given boiler plate CPU
design. The boiler plate design is written for basic instructions and the attached tutorial
videos shows how to extend the design to implement other instructions.

The top-level design file module structure of the RISC-V CPU implementation is shown in
the following table.

Table 1. Module Description

Signal Name Direction Description

clk Input Clock input for the module.
reset Input Reset signal for resetting the module.
External signal indicating memory write
Ext_MemWrite Input
operation.
Ext_WriteData Input External data to be written into data memory.
External Address for read/write operation in
Ext_DataAdr Input
memory.

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Signal Name Direction Description

MemWrite Output Signal indicating memory write operation.
WriteData Output Data to be written into data memory.
Address for read/write operation from/to the
DataAdr Output
data memory.
ReadData Output Data read from the data memory.
PC Output Value of Program counter for debugging.
Result Output ALU Result for debugging.

Approach
Implementing a RISC-V CPU in Verilog can be approached in several ways, each with its
own set of advantages and disadvantages.

Block Diagram Approach - In the block diagram approach, you break down the CPU into
functional blocks like the ALU, register file, control unit, and memory. You then connect
these blocks using wires to form the CPU. This approach offers excellent modularity and
readability. You can easily see the high-level structure of the CPU. However, it might involve

more wiring and can become complex for larger designs. 
Module Instantiation Approach - In this method, you create Verilog modules for each
functional blocks and instantiate these modules within the CPU module. This approach
provides modularity, similar to the block diagram approach, but also allows for a more
structured and scalable design. It simplifies the CPU module code and eases debugging.
On the downside, it requires creating and managing multiple module files.

Single File Approach - Here, you code the entire CPU in a single Verilog file, combining all
the components and logic. It's a compact approach, making it easier to manage and share.
However, it can become cumbersome for large and complex CPUs, leading to less
readable, maintainable code and much hard to debug.

You can use any one of the above-mentioned methods to complete this task with certain
restrictions and conditions, which are mentioned in the procedure section below.

Procedure
1. Download the t1c_riscv_cpu 🔗 quartus project and extract the file.

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2. Inside the t1c_riscv_cpu directory, Open the t1c_riscv_cpu.qpf file to launch the
Quartus software.

3. Now the main picture, find the attached t1c_riscv_cpu.v Verilog file with the
module declaration and other module instantiations. The top module is implemented
as shown in the following image.

 From the image it is clear that riscv_cpu module is connected is with the instruction 
memory and the data memory (via the external read/write access).

4. Also, you will find other Verilog design files like data_mem.v , instr_mem.v , and
riscv_cpu.v attached to the Quartus project.

Note: You are not allowed increase the size of the memory in data_mem.v and
instr_mem.v files.

Important: You are allowed to create and add new Verilog files but make sure you
are creating these files inside the code/components directory.

5. You can edit the riscv_cpu.v code to implement the RISC-V CPU using any of the
above mentioned approach. if required, You can use the codes provided in the
tutorial project.

Note: Go through the resources provided in RISC-V CPU Design, we have added a
t1c_riscv_cpu project. The project is implemented with single cycle RISC-V CPU but

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with base instructions, teams need to implement all the instructions mentioned in
the Table B1 on the RISC-V ISA PDF 🔗 into this design to complete the task.

Guide: If you plan to use the block diagram approach, follow the steps
mentioned below.

1. Make sure the BDF file has the same input and output signals as
mentioned in the t1c_riscv_cpu.v file.
2. After completing the BDF design, remove the attached riscv_cpu.v file
from the Quartus project and delete it from the directory.
3. Then convert your BDF to HDL design. Finally, change the file and module
names to riscv_cpu .

6. Once you have made the necessary changes, run "Analysis and Synthesis (Ctrl + K)"
to compile the Quartus Project. You should see the compilation success messages
in the Quartus message window. If you are getting any errors, debug the errors and
compile the project once again.

7. As explained in the video on the resources page, use ModelSim tool extensively to
debug the design and the testbench to identify the failing instructions.

 Note: you need to uncomment relevent test bench section in the tb.v inside the
.test folder for testing all instrustions.

8. If your design is correct you will see a No errors encountered, congratulations!
message at the transcript window, else you will see an Error message in the
transcript.

Note : If you can see the congratulations message in the ModelSim, your code can
still fail on the submission evaluator. Because not all the test cases is added to the
ModelSim simulation. Think about the robustness of the your design logic.

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Submission Instructions
To submit Task 1C follow the below-mentioned steps properly. 😅

 
Guide: If the size of your project directory is large 😢, download the above project zip
again and complete the above steps again. Then run the RTL simulation only once.

1. Create a new directory named mb_<Team_ID>_task1c as shown below.

If your Team ID = 6789 then your directory should be named as

mb_6789_task1c.

If your Team ID = 89 then your directory should be named as mb_0089_task1c.

2. Move or copy t1c_riscv_cpu project directory to this new directory.

Note: t1c_riscv_cpu project must be simulated using TestBench and NativeLink

Simulation (Modelsim) method. Submitting an un-simulated project directory will
result in zero marks.

3. Now create mb_<Team-ID>_task1c.zip file. For Team ID = 0005, mb_0005_task1c.zip

must be created. You can right click on the directory and click on compress to ZIP file

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to zip the file.

4. Now, You can submit this zip file through the portal 🔗. By clicking on Task 1C radio
button and upload the zip file.

…BestWishes!…

 

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