Programmable
Logic
Prgrammable Logic Organization
Pre-fabricated building block of many AND/OR gates (or NOR,
NAND)
"Personalized" by making or breaking connections among the gates
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
Programmable Array Block Diagram for Sum of Products Form
Basic Programmable Logic Organizations
Depending on which of the AND/OR logic arrays is
programmable, we have three basic organizations
ORGANIZATION
AND ARRAY
OR ARRAY
PAL
PROG.
FIXED
PROM
FIXED
PROG.
PLA
PROG.
PROG.
PLA Logic Implementation
Key to Success: Shared Product Terms
Equations
Example:
F0 = A + B C
F1 = A C + A B
F2 = B C + A B
F3 = B C + A
Personality Matrix
Product
term
AB
BC
AC
BC
A
Inputs
AB C
1 1 - 01
1 - 0
- 00
1 - -
Outputs
F0 F F
1 2
0 1 1
0 0 0
0 1 0
1 0 1
1 0 0
F3
0
Reuse
1
of
0
0 terms
1
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
0 = no connection to output
4
PLA Logic Implementation
Example Continued Un-programmed device
A
All possible connections are available
before programming
F0
F1
F2
F3
5
PLA Logic Implementation
A
Unwanted connections are "blown"
AB
BC
AC
BC
Note: some array structures
work by making connections
rather than breaking them
F0
F1
F2
F3
PLA Logic Implementation
Unprogrammed device
Alternative representation for
high fan-in structures
Short-hand notation so we don't
have to draw all the wires!
X at junction indicates a connection
A B C D
Programmed device
AB
Notation for implementing
AB
F0 = A B + A B
CD
F1 = C D + C D
CD
AB+AB CD+CD
PLA Logic Implementation
A B C
Multiple functions of A, B, C
ABC
A
B
F1 = A B C
C
A
F2 = A + B + C
F3 = A B C
ABC
F4 = A + B + C
ABC
F5 = A B C
ABC
ABC
F6 = A B C
ABC
ABC
ABC
F1 F2 F3 F4 F5
F6
PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept implemented by Monolithic Memories
- AND array is programmable, OR array is fixed at fabrication
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept Both AND and OR arrays are programmable
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PALs and PLAs
Of the two organizations the PLA is the most flexible
One PLA can implement a huge range of logic functions
BUT many pins; large package, higher cost
PALs are more restricted / you trade number of OR
terms vs number of outputs
Many device variations needed
Each device is cheaper than a PLA
10
PAL Logic Implementation
K-maps
Design Example: BCD to Gray Code Converter
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
00
CD
01
11
10
00
01
AB
00
CD
A
01
11
10
00
01
11
10
D
11
C
10
B
K-map for W
AB
00
CD
Minimized Functions:
W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD
B
K-map for X
A
01
11
10
00
01
AB
00
CD
A
01
11
10
00
01
11
10
D
11
C
10
B
K-map for Y
B
K-map for Z
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PAL Logic Implementation
A B
C D
A
BD
BC
Minimized Functions:
0
BC
W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD
0
0
0
B
C
0
0
ABCD
BCD
AD
BCD
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PAL Logic Implementation
Code Converter Discrete Gate Implementation
B
D
B
C
A
B
C
D
W
B
C
D
2
D
A
2
3
4
B
C
B
C
D
1: 7404 hex inverters
2,5: 7400 quad 2-input NAND
3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND
4 SSI Packages vs. 1 PLA/PAL Package!
13
PLA Logic Implementation
Another Example: Magnitude Comparator
AB
00
CD
A
01
11
10
AB
00
CD
01
11
10
00
00
ABCD
01
01
ABCD
11
11
ABCD
10
ABCD
D
C
C
10
AB
00
CD
AC
K-map for EQ
K-map for NE
AC
BD
A
01
11
10
00
01
AB
00
CD
01
11
10
00
01
D
11
ABD
BCD
D
BD
11
ABC
10
BCD
C
10
B
K-map for LT
B
K-map for GT
EQ NE LT
GT
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Complex Programmable Logic Devices
Complex PLDs typically combine PAL combinational logic
with FFs
Organized into logic blocks
Fixed OR array size
Combinational or registered output
Some pins are inputs only
Usually enough logic for simple counters, state
machines, decoders, etc.
e.g. 22G10, 20V8, etc.
15
Field Programmalble Gate Arrays (FPGAs)
FPGAs have much more logic than CPLDs
2K to >10M equivalent gates
Requires different architecture
FPGAs can be RAM-based or Flash-based
RAM FPGAs must be programmed at power-on
External memory needed for programming data
May be dynamically reconfigured
Flash FPGAs store program data in non-volitile memory
Reprogramming is more difficult
Holds configuration when power is off
16
FPGA Structure
Typical organization in 2-D array
Configurable logic blocks (CLBs) contain functional logic
Combinational functions plus FFs
Complexity varies by device
CLBs have connections to local neighbors
Horizontal and vertical channels use for long distance
Channel intersections have switch matrix
Usually have some additional C.L./FF in block
CLB interconnect is either local or long line
IOBs (I/O logic Blocks) connect to pins
17
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
IOB
CLB
IOB
IOB
Input/Output
Block
IOB
FPGA Structure
IOB
SM
CLB
SM
CLB
IOB
SM
CLB
SM
CLB
SM
IOB
Configurable
Logic
Block
CLB
SM
Switch
Matrix
SM
CLB
SM
SM
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
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