Introduction to VLSI Circuits and
Systems
Chapter 13
Memory and Programmable
Logic
Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Static RAM
SRAM Arrays
Dynamic RAM
ROM Arrays
Logic Arrays
Introduction to VLSI Circuits and Systems, NCUT
Static Random Access Memory,
SRAM
SRAM : cells use a simple bi-stable circuit to
hold a data bit
Three states: hold, write, and read operations
Access transistors (NMOS) provide W/R operations
(a) 6T cell
Access transistor
Figure 13.1 General SRAM cell
(b) 4T cell with poly
resistors
Figure 13.2 CMOS SRAM circuits
Introduction to VLSI Circuits and Systems, NCUT
SRAM (1/2)
Write 1: in worst case,
V1 = 0, V2 = VDD
(A/n = 2)
Why??
(W / L) nA
(13.1)
(W / L) n
Figure 13.3 6T SRAM cell design parameters
(a) Write 1 operation
Static Noise Margin: immunity
the coupled electromagnetic
signals (noise)
(b) Resistor model
Figure 13.4 Butterfly plot
Figure 13.5 Writing to an SRAM
Introduction to VLSI Circuits and Systems, NCUT
SRAM (2/2)
S: Source
D: Drain
S
D
D
Figure 13.7 A 2-port CMOS SRAM cell
Figure 13.6 Example of a basic 6-T SRAM cell layout
Figure 13.8 4-cell SRAM group
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Static RAM
SRAM Arrays
Dynamic RAM
ROM Arrays
Logic Arrays
Introduction to VLSI Circuits and Systems, NCUT
SRAM Arrays (1/4)
N 2m
Figure 13.9 High-level view of an
SRAM
Figure 13.11 Cell arrangement in a core region
Figure 13.12 Row driver circuit
Figure 13.10 Central SRAM block architecture
Introduction to VLSI Circuits and Systems, NCUT
SRAM Arrays (2/4)
Figure 13.13 Column MUX/DeMUX network for 8-bit words
Figure 13.14 Logic 1 column driver
Figure 13.15 Basic addressing scheme
Figure 13.16 Address latch circuit
Introduction to VLSI Circuits and Systems, NCUT
SRAM Arrays (3/4)
Figure 3.17 Pre-charge and I/O circuit for a single
column
Introduction to VLSI Circuits and Systems, NCUT
SRAM Arrays (4/4)
Figure 3.18 Expanded view of column circuitry
Figure 13.19 Write circuitry example
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Sensing Operation
(a) Circuit diagram
Figure 3.20 Example of a sensing
scheme for the read operation
v d (v v )
(b) Current flow
Figure 3.21 Single-ended differential amplifier
(13.5)
vout Av d A(v v ) (13.6)
I SS I D1 I D 2
(13.7)
Figure 3.22 Dual-amplifier scheme for
the sense amplifier network
Introduction to VLSI Circuits and Systems, NCUT
An example: A Drowsy SRAM
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Static RAM
SRAM Arrays
Dynamic RAM
ROM Arrays
Logic Arrays
Introduction to VLSI Circuits and Systems, NCUT
DRAM (1/3)
Dynamic RAM (DRAM)
Smaller than SRAM cells
Higher density storages arrays
As the central system memory in
microcomputer systems
Require more peripheral circuitry
Qs CsVs
(13.8)
Figure 13.23 1T DRAM
cell
For writing 1,
Vs Vmax VDD VTn
(13.9)
Qmax C s (V DD VTn )
(13.10)
(a) Write operation
(b) Hold
Figure 3.24 Write and hold operations in a DRAM cell
Introduction to VLSI Circuits and Systems, NCUT
DRAM (2/3)
Charge Leakage: When VG < VT, a
MOSFET is cutoff but still admits
small leakage currents
dQs
I L
dt
(13.11)
dV s
dt
(13.12)
Vs
(13.13)
I L C s
I L C s
Cs
IL
t h | t |
Vs
50 10 15
1 0.5 s
t h
9
1 10
f refresh
1
2t h
Figure 3.25 Charge leakage in a DRAM cell
(13.14)(hold time or retention time)
(13.15)(IL=1 nA, Cs=50 fF, and Vs=1 V)
(13.16)(refresh frequency)
Figure 3.26 Refresh operation summary
Introduction to VLSI Circuits and Systems, NCUT
DRAM (3/3)
Figure 3.28 A DRAM cell using a trench capacitor
Figure 3.26 Read operation in a DRAM cell
Q s C sV s
(13.17)
Qs C sV f C bitV f
(13.18)
Cs
V f
C s C bit
(13.19)
Vs
Figure 13.29 Visualization of stacked
capacitor structure
Introduction to VLSI Circuits and Systems, NCUT
DRAM Array and Peripheral
Circuit
Introduction to VLSI Circuits and Systems, NCUT
Divided-Word Line
Architectures
Figure 13.30 Basic for a dividedword line architecture RAM layout
Figure 13.31 Logic for a DWL design
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Static RAM
SRAM Arrays
Dynamic RAM
ROM Arrays
Logic Arrays
Introduction to VLSI Circuits and Systems, NCUT
ROM
Figure 13.33 Logic diagram for a NOR-based ROM
Figure 13.35 Map for ROM layout
Figure 13.34 ROM array using pseudo-nMOS circuitry
Figure 13.36 ROM layout based on FET map
Introduction to VLSI Circuits and Systems, NCUT
User-Programmable ROMs
Electrically-erasable EPROMs (E2PROMs) are used to store the BIOS code
in PC, and allow the user to update
(a) Symbol
(a) Normal VTn state
(b) Structure
(b) Increased VTn,H state
Figure 13.33 Logic diagram for a NOR-based ROM
Figure 13.37 Floating-gate MOSFET
Introduction to VLSI Circuits and Systems, NCUT
E2PROMs
Figure 13.39 A E2PROM word using floating-gate nFETs
Figure 13.40 Programming a floating-gate FET
Figure 13.41 Fowler-Nordheim tunnelling
Figure 13.42 EEPROM cell with write line
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Static RAM
SRAM Arrays
Dynamic RAM
ROM Arrays
Logic Arrays
Introduction to VLSI Circuits and Systems, NCUT
Programmable Logic Array,
PLA (1/2)
Figure 13.43 Structure of an AND-OR PLA
Figure 13.44 Logic gate diagram of the PLA
Introduction to VLSI Circuits and Systems, NCUT
Programmable Logic Array,
PLA (2/2)
(a) AND-OR logic
Figure 13.46 A dynamic CMOS PLA based on NOR gates
(b) NOR-based logic
Figure 13.45 NOR-gate PLA logic
Figure 13.47 Generic NOR-based logic plane
Introduction to VLSI Circuits and Systems, NCUT
Gate Array
(a) Structure
(b) Metal-active
(a) Gate array based
(c) Metal-metal
(b) NOR3 gate wiring
Figure 13.48 Transistor arrangement in a gate array
Figure 13.45 NOR-gate PLA logic
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