Pipelining and Vector Processing 1
CHAPTER 3
-T.KAVITHA,
ASSOC.PROF.
MVSREC
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Pipelining and Vector Processing 2
COMPLEX INSTRUCTION SET COMPUTERS: CISC
High Performance General Purpose Instructions
Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
2. Some instructions that performs a certain tasks are not
used frequently.
3. Many addressing modes are used (5 to 20)
4. Variable length instruction format.
5. Instructions that manipulate operands in memory.
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Pipelining and Vector Processing 3
CHARACTERISTICS OF RISC
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than micro programmed control
More RISC Characteristics
-A relatively large numbers of registers in the processor unit.
-Efficient instruction pipeline
-Compiler support: provides efficient translation of high-level Language
programs into machine language programs.
Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support
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Pipelining and Vector Processing 4
PIPELINING AND VECTOR PROCESSING
• Parallel Processing
• Pipelining
• Arithmetic Pipeline
• Instruction Pipeline
• RISC Pipeline
• Vector Processing
• Array Processors(refer book)
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Pipelining and Vector Processing 5 Parallel Processing
PARALLEL PROCESSING
Parallel processing is a term used to denote a large class of techniques that are
used to provide simultaneous data-processing tasks for the purpose of increasing
Computational speed of a computer system.
Instead of processing each instruction sequentially ,a parallel processing system is able
To perform concurrent data processing.
It can be achieved by two or more functional units (ALU’s).The amount of hardware
increases and the cost of the system too, but because of Technological developments , It
is feasible.
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
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Pipelining and Vector Processing 6 Parallel Processing
PARALLEL COMPUTERS
Architectural Classification
– Flynn's classification
» Based on the multiplicity of Instruction Streams and Data
Streams
» Instruction Stream
• Sequence of Instructions read from memory
» Data Stream
• Operations performed on the data in the processor
Number of Data Streams
Single Multiple
Number of Single SISD SIMD
Instruction
Streams Multiple MISD MIMD
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Pipelining and Vector Processing 7 Parallel Processing
COMPUTER ARCHITECTURES FOR PARALLEL
PROCESSING
Von-Neuman SISD Superscalar processors
based
Superpipelined processors
VLIW
MISD Nonexistence
SIMD Array processors
Systolic arrays
Dataflow
Associative processors
MIMD Shared-memory multiprocessors
Reduction
Bus based
Crossbar switch based
Multistage IN based
Message-passing multicomputers
Hypercube
Mesh
Reconfigurable
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Pipelining and Vector Processing 8 Parallel Processing
SISD COMPUTER SYSTEMS
Control Processor Data stream
Memory
Unit Unit
Instruction stream
Characteristics
- Standard von Neumann machine
- Instructions and data are stored in memory
- One operation at a time
Limitations
Von Neumann bottleneck
Maximum speed of the system is limited by the
Memory Bandwidth (bits/sec or bytes/sec)
- Limitation on Memory Bandwidth
- Memory is shared by CPU and I/O
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Pipelining and Vector Processing 9 Parallel Processing
MISD COMPUTER SYSTEMS
M CU P
M CU P
Memory
• •
• •
• •
M CU P Data stream
Instruction stream
Characteristics
- There is no computer at present that can be
classified as MISD
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Pipelining and Vector Processing 10 Parallel Processing
SIMD COMPUTER SYSTEMS
Memory
Data bus
Control Unit
Instruction stream
P P ••• P Processor units
Data stream
Alignment network
M M ••• M Memory modules
Characteristics
- Only one copy of the program exists
- A single controller executes one instruction at a time
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Pipelining and Vector Processing 11 Parallel Processing
MIMD COMPUTER SYSTEMS
P M P M ••• P M
Interconnection Network
Shared Memory
Characteristics
- Multiple processing units
- Execution of multiple instructions on multiple data
Types of MIMD computer systems
- Shared memory multiprocessors
- Message-passing multicomputers
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Pipelining and Vector Processing 12
Multiple-Functional Units
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Pipelining and Vector Processing 13
Applications of Parallel Processing
• Numerical weather forecasting
• Aerodynamics
• Finite element analysis
• Remote sensing applications
• Genetic engineering
• Computer assisted Tomography
• Weapon research
• Defence
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Pipelining and Vector Processing 14 Pipelining
PIPELINING
A technique of decomposing a sequential process into sub operations, with
each sub process being executed in a partial dedicated segment that
operates concurrently with all other segments.
Ai * Bi + Ci for i = 1, 2, 3, ... , 7
Ai Bi Memory Ci
Segment 1
R1 R2
Multiplier
Segment 2
R3 R4
Adder
Segment 3
R5
R1 Ai, R2 Bi Load Ai and Bi
R3 R1 * R2, R4 Ci Multiply and load Ci
R5 R3 + R4 Add
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Pipelining and Vector Processing 15 Pipelining
OPERATIONS IN EACH PIPELINE STAGE
Clock Segment 1 Segment 2 Segment 3
Pulse
Number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1
4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7
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Pipelining and Vector Processing 16 Pipelining
GENERAL PIPELINE
General Structure of a 4-Segment Pipeline
Clock
Input S1 R1 S2 R2 S3 R3 S4 R4
Space-Time Diagram
1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
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Pipelining and Vector Processing 17 Pipelining
PIPELINE SPEEDUP
n: Number of tasks to be performed
Conventional Machine (Non-Pipelined)
tn: Clock cycle
: Time required to complete the n tasks
= n * t n
Pipelined Machine (k stages)
tp: Clock cycle (time to complete each suboperation)
: Time required to complete the n tasks
= (k + n - 1) * tp The first task T1 req. a time equal to ktp to complete
its operation since there are k-segments in the pipe.
Speedup The remaining (n-1) tasks emerge from the pipe at the rate of
one task per clock cycle and will be completed in (n-1)tp.
Sk: Speedup
Sk = n*tn / (k + n - 1)*tp If ‘n’ becomes larger than K-1 and K+n-1 approaches
The value of ‘n’.
tn
lim Sk = ( = k, if tn = k * tp )
n tp
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Pipelining and Vector Processing 18 Pipelining
PIPELINE AND MULTIPLE FUNCTION UNITS
Example
- 4-stage pipeline
- subopertion in each stage; tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system; 20*4 = 80nS
Pipelined System
(k + n - 1)*tp = (4 + 99) * 20 = 2060nS
Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS
Speedup
Sk = 8000 / 2060 = 3.88
4-Stage Pipeline is basically identical to the system
Ii Ii+1 I i+2 I i+3
with 4 identical function units
Multiple Functional Units P1 P2 P3 P4
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Pipelining and Vector Processing 19 Arithmetic Pipeline
ARITHMETIC PIPELINE
Floating-point adder Exponents Mantissas
a b A B
X = A x 2a
Y = B x 2b
R R
[1] Compare the exponents
[2] Align the mantissa
[3] Add/sub the mantissa Compare Difference
Segment 1: exponents
[4] Normalize the result by subtraction
R
X=0.95404x103
Y=0.8200x102
Segment 2: Choose exponent Align mantissa
1.The two exponents are subtracted
in the first segment. R
2. The larger exponent is chosen as the
exponent of the result. Segment 3: Add or subtract
mantissas
3. The next segment shifts the mantissa
of Y to the right to obtain =0.0820x103
R R
4. This aligns the two mantissas under the
Same exponent. Adjust Normalize
Segment 4:
5. Addition of two mantissas in segment 3 exponent result
produces the sum. Z =1.0234x103;
R R
6.Normalize the result; Z =0.10234x104
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Pipelining and Vector Processing 20 Instruction Pipeline
INSTRUCTION CYCLE
Six Phases* in an Instruction Cycle
[1] Fetch an instruction from memory
[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place
* Some instructions skip some phases
* Effective address calculation can be done in
the part of the decoding phase
* Storage of the operation result into a register
is done automatically in the execution phase
==> 4-Stage Pipeline
[1] FI: Fetch an instruction from memory
[2] DA: Decode the instruction and calculate
the effective address of the operand
[3] FO: Fetch the operand
[4] EX: Execute the operation
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Pipelining and Vector Processing 21 Instruction Pipeline
INSTRUCTION PIPELINE
Execution of Three Instructions in a 4-Stage Pipeline
Conventional
i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX
Pipelined
i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX
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Pipelining and Vector Processing 22 Instruction Pipeline
INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE
Segment1: Fetch instruction
from memory
Decode instruction
Segment2: and calculate
effective address
yes Branch?
no
Fetch operand
Segment3: from memory
Segment4: Execute instruction
Interrupt yes
Interrupt?
handling
no
Update PC
Empty pipe
Step: 1 2 3 4 5 6 7 8 9 10 11 12 13
Instruction 1 FI DA FO EX
2 FI DA FO EX
(Branch) 3 FI DA FO EX
4 FI FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
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Pipelining and Vector Processing 23 Instruction Pipeline
MAJOR HAZARDS IN PIPELINED EXECUTION
Structural hazards(Resource Conflicts)
caused by access to memory by two segments at the same time.
Most of these conflicts can be resolved by using separate instruction
and data memories.
Data hazards (Data Dependency Conflicts)
An instruction scheduled to be executed in the pipeline requires the
result of a previous instruction, which is not yet available
Data dependency
R1 <- B + C ADD DA B,C +
R1 <- R1 + 1
INC DA bubble R1 +1
Control hazards
Branches and other instructions that change the PC
make the fetch of the next instruction to be delayed
JMP ID PC + PC Branch address dependency
bubble IF ID OF OE OS
Hazards in pipelines may make it Pipeline Interlock:
necessary to stall the pipeline Detect Hazards Stall until it is cleared
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Pipelining and Vector Processing 24 Instruction Pipeline
STRUCTURAL HAZARDS
Structural Hazards(Resource conflicts)
Occur when some resource has not been
duplicated enough to allow all combinations
of instructions in the pipeline to execute
Example: With one memory, a data and an instruction fetch
cannot be initiated in the same clock
i FI DA FO EX
i+1 FI DA FO EX
i+2 stall stall FI DA FO EX
The Pipeline is stalled for resource conflict
<- Two Loads with one port memory
-> Two-port memory will serve without stall
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Pipelining and Vector Processing 25 Instruction Pipeline
DATA HAZARDS
Data Hazards
Occurs when the execution of an instruction depends on the results of a
previous instruction
ADD R1, R2, R3
SUB R4, R1, R5
Data hazard can be dealt with either hardware techniques or software
technique
Hardware Technique
Interlock
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles.
Forwarding (bypassing, short-circuiting)
- Accomplished by a data path that routes a value from a source
(usually an ALU) to a user, bypassing a designated register. This
allows the value to be produced to be used at an earlier stage in the
pipeline than would otherwise be possible
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Cont……
• Software Technique (DELAY LOAD)
• The compiler is designed to detect a data conflict and
reorder instructions
• As necessary to delay the loading of the conflicting data
by inserting no-operation
• instructions. This method is called DELAY LOAD
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Pipelining and Vector Processing 27 Instruction Pipeline
CONTROL HAZARDS(Branching Difficulties)
Branch Instructions
- Branch target address is not known until
the branch instruction is decoded.
Branch
FI DA FO EX
Instruction
Next FI DA FO EX
Instruction
Target address available
- Stall -> waste of cycle times
Dealing with Control Hazards
* Prefetch Target Instruction
* Branch Target Buffer
* Loop Buffer
* Branch Prediction
* Delayed Branch
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Pipelining and Vector Processing 28 Instruction Pipeline
CONTROL HAZARDS
Prefetch Target Instruction
– Fetch instructions in both streams, instruction to be executed if
branch
not taken and the instruction if branch taken
– Both are saved until branch is executed. Then, select the right
instruction stream and discard the wrong stream
Branch Target Buffer(BTB; Associative Memory)
– Present in the fetch segment of the pipeline. It has entry of the
Address
of previously executed branches i.e. their Target instruction and
the next few instructions
– When fetching an instruction, search BTB.
– If found, fetch the instruction stream in BTB;
– If not, new stream is fetched and update BTB
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Loop Buffer(High Speed Register file)
– A variation of BTB. A register file maintained by the instruction fetch segment
of the pipeline.
– Register file stores the entire loop that allows to execute a loop
without accessing memory
Branch Prediction
– Uses additional logic to guess the outcome of the branch condition before it is
executed.
– The instruction is fetched based on the guess. Correct guess eliminates the
branch penalty
Delayed Branch
– Compiler detects the branch and rearranges the instruction sequence
by inserting useful instructions that keep the pipeline busy
in the presence of a branch instruction
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