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Neural Semiconductor Limited: Digital VLSI Testing Lecture-2 (Introduction)

This document discusses digital VLSI testing at various levels of abstraction, from chip to system level. It covers topics like simulation testing, quantifying quality metrics like yield and reject rates, system level operation factors like failure rates and reliability, and approaches to system level testing. The document also discusses test generation methods like exhaustive, functional and structural testing. It describes concepts like fault coverage, fault detection efficiency, and the goal of finding efficient test vectors. Common fault models and how they can reduce simulation time by removing equivalent faults are also summarized.

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Anik Paul
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306 views15 pages

Neural Semiconductor Limited: Digital VLSI Testing Lecture-2 (Introduction)

This document discusses digital VLSI testing at various levels of abstraction, from chip to system level. It covers topics like simulation testing, quantifying quality metrics like yield and reject rates, system level operation factors like failure rates and reliability, and approaches to system level testing. The document also discusses test generation methods like exhaustive, functional and structural testing. It describes concepts like fault coverage, fault detection efficiency, and the goal of finding efficient test vectors. Common fault models and how they can reduce simulation time by removing equivalent faults are also summarized.

Uploaded by

Anik Paul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Neural Semiconductor Limited

Digital VLSI Testing Seamless Technology Service

Lecture-2
(Introduction)
Design Verification

• Different level of abstraction

• Simulation used at various


levels to test
Quantifying Quality

Yield = Reject Rate

Passing Faulty Chip= Failing Good Chip=


Catastrophic Parametric
Electronic System Manufacturing

•System
• PCB
• VLSI
• PCB and VLSI having similar
kind of fabrication

• Possible defects
System Level Operation

• Faults during system operation

• Exponential Failure Law

• Reliability
• Normal Operation Probability,

• Failure Rate , [ is individual component failure rate]


System Level Operation (Contd.)

•  Mean time between failure:

• Repair time R, [is repair rate]

• Mean time to repair,

• System Availability =
System Level Testing

• Testing is required to ensure system availability

• Types of system level testing:

• Online Testing

• Offline Testing
Test Generation

• Approaches to test:

• Exhaustive Testing: Using all possible test patterns.

• Functional Testing: Using all entries of truth table for the combinational
circuit.

• Structural Testing: Selecting specific test patterns, costing fault


coverage.
Test Generation (Contd.)

•  Fault coverage = [for a set of test patterns]

• Fault detection efficiency =

• Reject rate =
Test Generation (Contd.)

• For example if a PCB has 40 chips, each with 90% fault coverage
and 90% yield, has a reject rate of 41.9%, almost 16-17 chips
will be rejected among the 40 chips.

Or 419,000 defective parts per million (PPM).


Test Generation (Contd.)

• Goal – Finding an efficient set of test vectors.

• Fault Simulation

• Good Fault Model


• Computationally efficient
• Accurately reflects defect behaviour

• No single fault model works for all possible defects.


Fault Models

• A given fault model can have k faults


• k = 2 for most of the fault models

• Having n possible fault sites, fault types can be

• Single Fault Model: Whole circuit has only 1 fault. #of faults = k X n

• Multiple Fault Model: Circuit can have more than 1 fault sites.
#of faults = (k + 1)n - 1
Fault Models

• Equivalent Faults
• Faults that have identical behaviour for all possible input patterns
• Only one from a set of equivalent faults need to be simulated

• Fault Collapsing
• Removing Equivalent Faults
• Except for the one to be simulated
• Reduces Total Number of Faults
• Reduces fault simulation time
• Reduces test pattern generation time
Reference

• Lecture Link:

https://www.youtube.com/watch?v=JnwoEXs8ezI
Thank You
info@neural-semiconductor.com

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