Experiment 9

Using Embedded
Microcontroller Cores to
Implement Complex Digital
Systems

ECE 448 – FPGA and ASIC Design with VHDL George Mason University
 PIC Microcontroller implemented inside of
an FPGA device
FPGA

CLK

PIC RESET
µController
STROBE = PORTC(0)
PORTC

PORTB PORTA

7-Seg Decoder

Display PORTA

ECE 448 – FPGA and ASIC Design with VHDL 2

 PIC Microcontroller Core
MCLR CLK

PROGRAM

CONTROL
PICROM 8 P UNIT
256 x 12 Addr C Address Bus
Data
DATA
12 REGFILE
R8
Instruction Decoder Fsel

8 4 8 R31
CONSTANTS OPCODES FSR
Din Dout

Data Bus 8
W ALU

EXTENDED 4 8 8
COMPUTATIONS ALU PORTA PORTB PORTC

4 8 8
ECE 448 – FPGA and ASIC Design with VHDL 3
 Flowchart of our PIC program

RESET

Set Port Directions

Sum <= ‘0’

Counter <= ‘0’ Wait for a rising edge at
Port C(0)
Wait for a rising edge at
Port C(0)
Port B <= Sum(3 downto 0)

N Port B <= Port A

Sum <= Sum + Port A Wait for a rising edge at
Counter <= Counter + 1 Port C(0)

Y Port B <= Sum(7 downto 4)

Counter = 8?

ECE 448 – FPGA and ASIC Design with VHDL 4

 Selected Registers of PIC
ADDR
 W Working Register (Accumulator)

 PC Program Counter

05 PORTA
06 PORTB Bidirectional
07 PORTC Input/Output Ports

08 R8
09 R9
0A R10
. Register File
. (General Purpose
Registers)
1E R30
1F R31

 TRISA
Direction Registers
 TRISB
for Ports A, B & C
 TRISC

ECE 448 – FPGA and ASIC Design with VHDL 5

 Selected PIC Instructions (1)

MOVF f, d
MOVF f, 1
f f  <8,31>
MOVF f, 0
k  <0,255>
W

MOVWF f MOVLW k
W k
MOVWF f MOVLW k

f W

ECE 448 – FPGA and ASIC Design with VHDL 6

 Selected PIC Instructions (2)
0
CLRF f CLRF f

f f  <8,31>

0
CLRW CLRW

ECE 448 – FPGA and ASIC Design with VHDL 7

 Selected PIC Instructions (3)

INCF f, d

+1
INCF f,1

INCF f,0

ECE 448 – FPGA and ASIC Design with VHDL 8

 Selected PIC Instructions (4)

ADDWF f, d

W f

ADDWF f, 0 ADDWF f, 1
+

ECE 448 – FPGA and ASIC Design with VHDL 9

 Selected PIC Instructions (5)

ANDWF f, d

W f

ANDWF f, 0 ANDWF f, 1
and

ECE 448 – FPGA and ASIC Design with VHDL 10

 Selected PIC Instructions (6)

SWAPF f, d
SWAPF f, 1

fH fL
SWAPF f, 0

ECE 448 – FPGA and ASIC Design with VHDL 11

 Selected PIC Instructions (7)
CALL label GOTO label

RETLW
CALL label
CALL label GOTO label

label
label label

RETLW

ECE 448 – FPGA and ASIC Design with VHDL 12

 Selected PIC Instructions (8)

BTFSC f, b
f

7 b 0

f(b) = 0? BTFSC f, b
No
Next instruction
Yes
After-next Instruction

ECE 448 – FPGA and ASIC Design with VHDL 13

 Selected PIC Instructions (8)

BTFSS f, b
f

7 b 0

f(b) = 1? BTFSS f, b
No
Next instruction
Yes
After-next Instruction

ECE 448 – FPGA and ASIC Design with VHDL 14

 Selected PIC Instructions (9)

TRIS f W

TRIS PORTA TRIS PORTC

TRIS PORTB

TRISA TRISB TRISC

4 8 8

1 – Input port bit direction

0 – Output port bit direction

ECE 448 – FPGA and ASIC Design with VHDL 15

 PIC Programming Environment
Source File in the PIC
*.ASM
Assembly Language

MPASM

HEX File *.HEX *.LST Listing File

MPSIM

ECE 448 – FPGA and ASIC Design with VHDL 16

 Block RAMs in Spartan III FPGAs

Configurable
Logic
Blocks

I/O
Block RAMs

Block RAMs
Blocks

Block
RAMs

ECE 448 – FPGA and ASIC Design with VHDL 17

 Spartan-3 Block RAM Amounts

ECE 448 – FPGA and ASIC Design with VHDL 18

 Block RAM Port Aspect Ratios

used to implement PICROM 256x12

ECE 448 – FPGA and ASIC Design with VHDL 19

 Block RAM Port Aspect Ratios
1 2
0 4
0
0

8k x 2 4k x 4

4,095

16k x 1 8,191
8+1
0
2k x (8+1)
2047

16+2
0
1023
1024 x (16+2)
16,383

ECE 448 – FPGA and ASIC Design with VHDL 20

 Dual Port Block RAM

ECE 448 – FPGA and ASIC Design with VHDL 21

 Dual-Port RAM 1024 x 18
RAMB4_S4_S16
WEA
ENA
Port A In RSTA DOA[17:0]
Port A Out
1K-Bit Depth CLKA 18-Bit Width
ADDRA[9:0]
DIA[17:0]

WEB
ENB

Port B In RSTB DOB[17:0]

Port B Out
1k-Bit Depth CLKB 18-Bit Width
ADDRB[9:0]
DIB[17:0]

• Each port can be configured with a different data bus

width
• Provides easy data width conversion without any
additional logic
ECE 448 – FPGA and ASIC Design with VHDL 22
Dual-Port RAM used as 1024x18 ROM

RAMB4_S4_S16
0 WEA
1 ENA
Clk_ROM 0 RSTA DOA[17:0] Data[17:0]
CLKA
ADDRA[9:0]
Addr[9:0] DIA[17:0]

WEB
All inputs ENB

of PORT B RSTB DOB[15:0] Outputs of PORT B

CLKB
and data inputs ADDRB[7:0] left unconnected
DIB[15:0]
of PORT A
connected to 0

ECE 448 – FPGA and ASIC Design with VHDL 23

 Contents of the Program Memory
16 bits stored
ADDR
00 0040
01 0006
02 0068
03 006A
04 0917
……. 256 memory
…. locations
FD 0000
FE 0000
FF 0000

12 bits read

ECE 448 – FPGA and ASIC Design with VHDL 24

 Initializing Block RAMs in VHDL
INIT_00 : BIT_VECTOR := X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040";
INIT_01 : BIT_VECTOR := X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026";
INIT_02 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
……………………………………………………………………………………………………………………………………
INIT_0F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000")
DATA
ADDRESS
INIT_00 014A 0C0F 0917 006A 0068 0006 0040
ADDRESS 0F 0E 04 03 02 01 00
INIT_01 0000 0000 014A 0C0F 03AA 0917 0026
ADDRESS 1F 1E 14 13 12 11 10

Addresses are
shown in red and
data corresponding
to the same
memory location is
shown in black
INIT_0F 0000 0000 0000 0000 0000 0000 0000
ADDRESS FF FE F4 F3 F2 F1 F0

ECE 448 – FPGA and ASIC Design with VHDL 25

 Questions?

ECE 448 – FPGA and ASIC Design with VHDL 26