MICROCONTROLLER
2. ARM
Microcontroller
HISTORY OF ARM Ltd
Founded in November 1990 by a small group of engineers
- Advanced RISC Machines
Company headquarters in Cambridge, UK
- Processor design in Cambridge, Austin, and Sophia Antipolis
- Sales, support, and engineering offices all over the world
Best know for its range of RISC processor core designs
- Also produce software tools, models, cell libraries for partners
ARM does not manufacture silicon
ARM partners ship billion chips with ARM processors each year
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INSTRUCTION SET
RISC (Reduced instruction set CISC (Complex instruction set
computers) computers)
• 1 instruction = 1 operation • complex instructions are built
• all instructions execute in the same directly into the hardware
time • resembles a higher level language
• more RAM is needed to store more • 1 instruction = many operations
line of code • does not require the programmer
• Require less transistor on processor to explicitly call any loading or
EX: storing functions
LOAD A, 2:3 • More transistor on processor, less
LOAD B, 5:2 RAM needed
PRO A, B Ex:
STORE 2:3, A MULT 2:3, 5:2
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INSTRUCTION SET
Can we make the
whole process faster ?
Significantly speedup
http://www.ece.arizona.edu/~ece462/Lec03-pipe/ the operation!
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Why ARM?
Arm
Five biggest MCU suppliers accounted for 82% of
sales
(IC Insights’ 2022 report)
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Why ARM?
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ARM Cortex family
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ARM Cortex family
ARM Cortex™-A family:
Applications processors for feature-rich OS and 3rd party
applications
ARM Cortex-R family:
Embedded processors for real-time signal processing,
control applications
ARM Cortex-M family:
Microcontroller-oriented processors for MCU, ASSP, and
SoC applications
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Cortex-M family
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Cortex-M family
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Cortex-M Instruction Set
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Cortex-M4 processor
(Refer to the Cortex-M4 Datasheet for more detail) 12
Cortex M4 Memory Organization
Code Region (0x00000000 - 0x1FFFFFFF)
• Up to 512MB
• Store program code, can also put data here
• Store vector table at address 0x00000000
SRAM Region (0x20000000 - 0x3FFFFFFF)
• Up to 512MB
• Store data, can also put program code here
Peripheral Region (0x40000000 -0x5FFFFFFF)
• Up to 512MB
• Primarily used for peripherals
RAM Region (0x60000000 - 0x9FFFFFFF)
• consists of two 512 MB blocks
• primarily used to stored data
• The only differences between the two halves of the RAM region
are the memory attributes 13
Cortex M4 Memory Organization
Device Region (0xA0000000 - 0xDFFFFFF)
• consists of two 512 MB memory blocks
• primarily used for peripherals
• two halves of the device region have different memory
attributes.
Internal Private Peripheral Bus (0xE0000000 -
0xE00FFFFF)
• allocated for peripherals inside the processor
• Size is 1 MB
System Space (0xE0100000 - 0xFFFFFFFF)
• Up to 512MB
• Reserve for microcontroller vendor specific usages
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Cortex-M bus system
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Cortex-M bus system
Bus system in Cortex-M consists:
• 32-bit system bus
• 32-bit peripheral bus
The system bus
• Based on a AHB protocol
• Connect the processor with different types of memories
• support read/write transfers with 32-, 16-, and 8-bit data
The peripheral bus
• Based on APB protocol
• The APB is connected to the AHB-Lite via a bus bridge
• Can run at a different clock speed compared to the AHB system bus
In real applications
• Peripheral bus segments may run at different clock frequencies
• Some part of the system may run in a slower speed to achieve power reduction
• Application might need to initialize clock control hardware before accessing main
program
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Cortex-M bus system
Bus matrix
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Bus matrix
S0: I-bus
• This bus is used by the core to fetch
instructions.
S1: D-bus
• This bus is used by the core for literal
load data and debug access.
S2: S-bus
• This bus is used by the core to
access data located in a peripheral or
SRAM area.
S3, S4: DMA-bus
• This bus connects the DMA to the
BusMatrix.
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