Module IV

Memory Organization
 Topics to be covered
 Memory Hierarchy
 Main Memory
 Auxiliary Memory
 Associative Memory
 Cache Memory
 Virtual Memory
 Memory Management Hardware

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 Memory Hierachy
 Memory unit is an essential component in any digital
computer since it is needed for storing programs and
data.

 Not all accumulated information is needed by the CPU

at the same time.

 Therefore, it is more economical to use low cost

storage devices to serve as a back up for storing the
information that is not currently used by the CPU.

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 This Memory Hierarchy Design is divided into 2 main types:
 External Memory or Secondary Memory –
Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e.
peripheral storage devices which are accessible by the
processor via I/O Module.
 Internal Memory or Primary Memory –
Comprising of Main Memory, Cache Memory & CPU registers.
This is directly accessible by the processor.

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 Capacity:
It is the global volume of information the memory can store.
As we move from top to bottom in the Hierarchy, the capacity
increases.
 Access Time:
It is the time interval between the read/write request and the
availability of the data. As we move from top to bottom in the
Hierarchy, the access time increases.
 Cost per bit:
As we move from bottom to top in the Hierarchy, the cost per
bit increases i.e. Internal memory is costlier than external
memory.

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 Memory Hierarchy in a computer
system

Auxiliary Memory

Magnetic

Tapes Main
I/O Processor Memory

Magnetic
Disks
Cache
CPU Memory

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Memory Hierarchy

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 Main Memory

ROM – Read Only Memory

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RAM Chip

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 RAM Chip

27 = 7-bit address lines

• The capacity of the memory is 128 words of eight bits per word.

• This requires a 7-bit address and 8 bit bidirectional data bus.

• The read and write inputs specify the memory operation.

• The two chip selects (CS) control inputs are for enabling the chip
only when it is selected by the microprocessor. The availability of
more than one control input to select the chip facilitates the
decoding of the address lines when multiple chips are used
11 in the
microcomputer.
Function Table (RAM chip)

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 Operation of RAM chip
 The unit is in operation only when CS1=1 and CS2’=0.
 If the chip select inputs are not enabled , or they are
enabled but Read or Write inputs are not enabled, the
memory is inhibited and data bus is in high impedance
state.
 When CS1=1 and CS2’=0, the memory can be placed in a
write or read mode.
 When the WR input is enabled, the memory stores a
byte from the data bus into a location specified by the
address input lines.
 When the RD input is enabled , the content of the
selected byte is placed onto the data bus.

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ROM chip

29 = 9 bit address lines

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 ROM chip
 A ROM chip is organized externally in a similar manner.
 Since a ROM can only be read so data bus can only be in
an output mode.
 For the same size chip , it is possible to have more bits
of ROM than of RAM because the internal binary cells in
ROM occupy less space than in RAM. So here a 512byte
ROM is represented , while RAM has only 128 bytes.
 The 9 address lines in the ROM specify any one of the
512 bytes stored in it.
 There is no need for a read or write control because the
unit can only be read.
 So, when the chip is enabled by two select inputs , the
byte selected by the address lines appears on the bus.

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Memory Address Map
 The addressing of memory can
be established by means of a
table that specifies the memory
address assigned to each chip.

 The table, called a memory

address map, is a pictorial
representation of assigned
address space for each chip in
the system.

 Let’s take an example :

 A computer system needs 512
bytes of RAM and 512 bytes of
ROM . The memory address map
for this configuration is shown
in the table:
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 Memory Address Map
 The component column specifies whether a RAM or ROM chip is
used.
 The hexadecimal address column assigns a range of hexadecimal
equivalent address for each chip.
 Address bus lines are listed in the third column. Although there
are 16 lines in the address bus, table shows only 10 lines. Other 6
are not used in this example and are assumed to be zero.
 RAM chips have 128 bytes and need 7 address lines. ROM chip has
512 bytes and need 9 address lines.
 X’s are always assigned to low order bus lines, lines 1-7 for RAM
and 1-9 for ROM.
 Bus lines 8 and 9 are used to represent 4 distinct binary
combinations.
 Distinction between RAM and ROM chip is done using bus line 10.
When line 10 is 0, CPU selects a RAM and when it is 1 , CPU
selects a ROM.
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Memory connection to CPU

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 Memory connection to CPU
 RAM and ROM chips are connected to CPU through the data
and address buses.
 The low-order lines in the address bus select the byte within
the chips and other lines in the address bus select a
particular chip through its chip select inputs.
 The configuration used here gives the memory capacity of 512
bytes of RAM and 128 bytes of ROM.
 Each RAM receives the 7 low order bits of the address bus to
select one of 128 possible bytes.
 The particular RAM chip selected is determined from lines 8
and 9 in the address bus.This is done through a 2X4 decoder
whose outputs go to the CS1 inputs in each RAM chip.

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 Memory connection to CPU

 RD and WR outputs from the microprocessor are applied to

the inputs of each RAM chip.
 The selection between RAM and ROM is achieved through
bus line 10.RAMs are selected when the bit in this line is 0,
and the ROM when the bit is 1.
 The other chip select input in the ROM is connected to the
RD control line for the ROM chip to be enabled only during
the read operation.
 Address lines 1-9 are applied to the input address of ROM
without going through the decoder. This assigns addresses 0
to 511 to RAM and 512 to 1023 to ROM.

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 Numericals
Q1:

Sol:

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Numericals

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Solution

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 Reference

 Morris Mano: Computer System Architecture

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 THANK YOU

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