Field Programmable Gate Arrays
FPGA
Field Programmable Gate Array
New Architecture
‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Large Number of Logic Block ‘Islands’
1,000 … 100,000+
in a ‘Sea’ of Interconnects
FPGA Architecture
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Logic Blocks
Logic Functions implemented in Lookup Table LUTs
Multiplexers (select 1 of N inputs)
Flip-Flops. Registers. Clocked Storage elements.
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric Logic Block
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Lookup Tables LUTs
LUT contains Memory Cells to implement small logic functions
Each cell holds ‘0’ or ‘1’ .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
a 4-input
LUT
b
3 – 6 Inputs c
y
mux
d flip-flop
q
e
clock
clock enable
set/reset SRAM
Static Random Access Memory
SRAM
SRAM cells
Multiplexer MUX
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Logic Blocks
Larger Logic Functions built up by connecting many Logic
Blocks together
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Clocked Logic
Flip Flops on outputs. CLOCKED storage elements.
Sequential Logic Functions (cf Combinational Logic LUTs)
Pipelines. Synchronous Logic Design
FPGA Fabric driven by Global Clock (e.g. BX frequency)
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
Clock
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
FPGA Design Synchronous Logic
Pipelining Logic
Combinational Logic
Combinational Combinational Combinational
Logic Logic Logic
Data In etc. Result
Three levels of logic
AND
& OR
From previous To next bank
| NOR
bank of registers of registers
|
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
FPGA Design Synchronous Logic
Pipelining Logic
Combinational Logic Stored in Registers.
Clocked Logic (e.g. at LHC BX 40 MHz)
Combinational Combinational Combinational
Logic Logic Logic
Data In etc.
Registers Combinational Registers Combinational Registers
Logic Logic
Data In Once Pipeline Full
etc. New Result every Clock Period
Clock
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
FPGA Design Synchronous Logic
Pipelining
Combinational and Sequential Logic.
Clocked Logic (e.g. at LHC BX 40 MHz)
Combinational Combinational Combinational
Logic Logic Logic
Data In etc.
Registers Combinational Registers Combinational Registers 16-bit SR
16x1 RAM
Logic Logic a 4-input
LUT
b
y
c
mux
d flip-flop
Data In q
etc. e
clock
clock enable
set/reset
Clock
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Clocked Logic
FPGA Fabric driven by Global Clock (e.g. BX frequency)
Registers Combinational Registers Combinational Registers
Logic Logic
Data In
Register Transfer Logic RTL
etc.
Clock
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
Clock
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Routing
Connections Routing signals between Logic Blocks
Determined by SRAM cells
SRAM
Special Routing for Clocks
Around Fabric Edges Configurable Input Output I/O Blocks
100’s – 1,000 Pins
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Configuring an FPGA
Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Loses configuration when board power is
turned off.
Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. ROM or Digital Camera card
Configuration takes ~ secs
JTAG Port
Configuration data in
Configuration data out
= I/O pin/pad
Programming = SRAM cell
Bit File
SRAM
JTAG Testing
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Designing Logic with FPGAs
High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesise) into Netlist.
Boolean Logic Gates. Design Flow
Target FPGA Fabric Schematic Gate-level
capture netlist
Mapping BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
Routing
OUTPUT Q, N_Q;
WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR (IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
Bit File for FPGA
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Packing
Commercial CAE Tools Place-and-
Route Timing analysis
(Complex & Expensive) and timing report
Fully-routed physical Gate-level netlist
(CLB-level) netlist for simulation
Logic Simulation SDF (timing info)
for simulation
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Field Programmable Gate Arrays
FPGA
Large Complex Functions
Programmability, Flexibility.
Massively Parallel Architecture
Processing many channels simultaneously cf MicroProcessor
sequential processing
Fast Turnaround Designs
SRAM Based. Standard IC Manufacturing Processes (Memory Chips)
Leading Edge of Moore’s Law
Mass produced. Inexpensive.
Many variants. Sizes. Features.
Not Radiation Hard
Power Hungry
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
Trends
State of Art is 65nm on 300 mm wafers
Top of range 100,000+ Logic Blocks
1,000 pins (Fine Pitched Ball Grid Arrays)
Logic Block cost ~ 1$ in 1990 ; $0.002 in 2005
1000x
Challenges
XC4000 &
Spartan
100x
Power. Leakage currents. Virtex-4
CLB Capacity Virtex-II &
Speed Virtex-II Pro
Signal Integrity Power per MHz
Price
Virtex &
Virtex-E
ITRS Roadmap
10x
Design Gap Spartan-2
CAE Tools XC4000 Spartan-3
1x
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
The Design Warrior’s Guide to FPGAs
john.coughlan@rl.a Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
c.uk
