VHDL Coding Syntax

___________________________________________________________________________VHDL Syntax
1 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Dr. V. P. Shetkari Shikshan Mandal’s
Padmabhooshan Vasantraodada Patil Institute of Technology,
Budhgaon-416304
Digital System Design
LAB MANUAL
Prepared by
Mr. A. B. Shinde
Assiatant Profesor,
Electronics Engineering
abshinde.eln@pvpitsangli,edu.in
Department of Electronics Engineering
2013-14

___________________________________________________________________________VHDL Syntax
ADDER / SUBTRACTOR
process (<input1>, <input2>)
begin
if <add_sub> = '1' then
<addsub_output> <= <input1> + <input2>;
else
<addsub_output> <= <input1> - <input2>;
end if;
end process;
Adder with carry in
<output> <= <input1> + <input2> + <one_bit_carry_in>;
Adder with carry out
<temp_value> <= <input1> + <input2>;
<output_sum> <= <temp_value>((<adder_width>-1) downto 0);
<carry_out> <= <temp_value>(<adder_width>);
Simple Adder
<output> <= <input1> + <input2>;

___________________________________________________________________________VHDL Syntax
COMPARATOR
Equal
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> = <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Greater than
begin
<output> <= '0';
if ( <input1> > <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Greater than or equal
begin
<output> <= '0';
if ( <input1> >= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
Less than
begin
<output> <= '0';
if ( <input1> < <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Less than or equal
begin
<output> <= '0';
if ( <input1> <= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Not equal
begin
<output> <= '0';
if ( <input1> /= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
Synchronous Multiplier
process (<clock>)
begin
if <clock>='1' and <clock>'event then
<output> <= <input1> * <input2>;
end if;
end process;
Asynchronous Multiplier
<output> <= <input1> * <input2>;
Subtractor
<output> <= <input1> - <input2>;
Logic gates
AND
<output> <= <input1> and <input2> and <input3>;
INVETER
<output> <= not <input1>;
NAND
<output> <= not (<input1> and <input2> and <input3>);
OR
<output> <= <input1> or <input2> or <input3>;
NOR
<output> <= not (<input1> or <input2> or <input3>);
XNOR
<output> <= not(<input1> xor <input2> xor <input3>);
XOR
<output> <= <input1> xor <input2> xor <input3>;

___________________________________________________________________________VHDL Syntax
Counters
Binary Down Counter
process (<clock>)
begin
if <clock_enable>='1' then
<count> <= <count> - 1;
end if;
end if;
end process;
CE, Asynchronous active high Reset
process (<clock>, <reset>)
begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
end if;
end if;
end process;
CE Asynchronous active low Reset
begin
if <reset>='0' then
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
begin
if <reset>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
end if;
end if;
end if;
end process;
begin
if <reset>='0' then
<count> <= <input>;
else
end if;
end if;
end if;
end process;
Simple Counter
process (<clock>)
begin
end if;
end process;

___________________________________________________________________________VHDL Syntax
Up Counters
process (<clock>)
begin
if <count_direction>='1' then
<count> <= <count> + 1;
else
end if;
end if;
end if;
end process;
begin
if <reset>='1' then
else
end if;
end if;
end if;
end process;
begin
if <reset>='0' then
else
end if;
end if;

___________________________________________________________________________VHDL Syntax
end if;
end process;
begin
if <reset>='1' then
<count> <= <input>;
else
else
end if;
end if;
end if;
end if;
end process;
begin
if <reset>='0' then
<count> <= <input>;
else
else
end if;
end if;
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
process (<clock>)
begin
else
end if;
end if;
end process;
Gray Code Converter
<next_binary_count> <= <binary_count> + 1;
begin
if ( <reset> = '1') then
<binary_count> <= (others => '0');
<gray_count> <= (others =>'0');
elsif ( <clock>'event and <clock> ='1') then
<binary_count> <= <next_binary_count>;
<gray_count> <= (('0' & next_binary_count(<width-1> downto 1))
XOR <next_binary_count>);
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
LFSR
16 bit
begin
<reg_name> <= (others => '0');
<reg_name>(15 downto 1) <= <reg_name>(14 downto 0) ;
<reg_name>(0) <= not(<reg_name>(15) XOR <reg_name>(14) XOR
<reg_name>(13) XOR <reg_name>(4));
end if;
end if;
end process;
32 bit
begin
<reg_name>(2) XOR <reg_name>(1));
end if;
end if;
end process;
4 bit
begin
<reg_name>(0) <= not(<reg_name>(4) XOR <reg_name>(3));
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
8 bit
begin
<reg_name>(4));
end if;
end if;
end process;
Decoders
2:4
process(<clock>,<reset>,<input>)
begin
<output> <= "0000";
case <input> is
when "00" => <output> <= "0001";
when "01" => <output> <= "0010";
when "10" => <output> <= "0100";
when "11" => <output> <= "1000";
when others => "0000";
end case;
end if;
end process;

___________________________________________________________________________VHDL Syntax
3:8
begin
<output> <= "00000000";
case <input> is
when "000" => <output> <= "00000001";
when "001" => <output> <= "00000010";
when "010" => <output> <= "00000100";
when "011" => <output> <= "00001000";
when "100" => <output> <= "00010000";
when "101" => <output> <= "00100000";
when "110" => <output> <= "01000000";
when "111" => <output> <= "10000000";
when others => "00000000";
end case;
end if;
end process;
Encoders
2:4
begin
<output> <= "00";
case <input> is
when "0001" => <output> <= "00";
when "0010" => <output> <= "01";
when "0100" => <output> <= "10";
when "1000" => <output> <= "11";
end case;
end if;
end process;

___________________________________________________________________________VHDL Syntax
8:3
begin
<output> <= "000";
case <input> is
when "00000001" => <output> <= "000";
when "00000010" => <output> <= "001";
when "00000100" => <output> <= "010";
when "00001000" => <output> <= "011";
when "00010000" => <output> <= "100";
when "00100000" => <output> <= "101";
when "01000000" => <output> <= "110";
when "10000000" => <output> <= "111";
end case;
end if;
end process;
D-FF
process (<clock>)
begin
if <clock>'event and <clock>='0' then
<output> <= <input>;
end if;
end process;
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='0') then
end if;
end process;

___________________________________________________________________________VHDL Syntax
begin
if <reset>='1' then
<output> <= '0';
if <clock_enable> = '1' then
end if;
end if;
end process;
begin
if <reset>='0' then
<output> <= '0';
end if;
end process;
begin
if <reset>='0' then
<output> <= '0';
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='1' then
<output> <= '0';
else
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
process (<clock>)
begin
if <reset>='1' then
<output> <= '0';
elsif <clock_enable> ='1' then
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='0' then
<output> <= '0';
else
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='0' then
<output> <= '0';
end if;
end if;
end process;
T-FF
process (<clock>)
begin
<output> <= not(<output>);
end if;
end process;

___________________________________________________________________________VHDL Syntax
begin
if <reset>='1' then
<output> <= '0';
end if;
end process;
begin
if <reset>='1' then
<output> <= '0';
end if;
end if;
end process;
begin
if <reset>='0' then
<output> <= '0';
end if;
end process;
begin
if <reset>='0' then
<output> <= '0';
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
process (<clock>)
begin
if <reset>='1' then
<output> <= '0';
else
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='1' then
<output> <= '0';
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='0' then
<output> <= '0';
else
end if;
end if;
end process;
process (<clock>)
begin
if <reset>='0' then
<output> <= '0';
end if;

___________________________________________________________________________VHDL Syntax
end if;
end process;
Logical Shifters
2bit
--use IEEE.numeric_std.all;
begin
<output> <= (others => '0');
case <selector> is
when "00" => <output> <= <input> ;
when "01" => <output> <= <input> sll 1;
when others => <output> <= <input> ;
end case;
end if;
end process;
3 bit
begin
case <selector> is
end case;
end if;
end process;

___________________________________________________________________________VHDL Syntax
4 bit
begin
case <selector> is
end case;
end if;
end process;
HEX to SEVEN SEGMENT CONVERSION
-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
-- LED: out STD_LOGIC_VECTOR (6 downto 0);
-- segment encoinputg
-- 0
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- 3

___________________________________________________________________________VHDL Syntax
with HEX SELect
LED<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
Barrel Shifter
-- 16-bit right shift barrel shifter
-- SEL: in STD_LOGIC_VECTOR(3 downto 0);
-- B_INPUT: in STD_LOGIC_VECTOR(15 downto 0);
-- B_OUTPUT: out STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal SEL_A, SEL_B: STD_LOGIC_VECTOR(1 downto 0);
signal C: STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following after the 'begin' keyword**
SEL_A <= SEL(1 downto 0);
SEL_B <= SEL(3 downto 2);
process(SEL_A,B_INPUT)
begin
case SEL_A is
when "00" => --shift by 0
C <= B_INPUT;
C(15) <= B_INPUT(0);

___________________________________________________________________________VHDL Syntax
C(14 downto 0) <= B_INPUT(15 downto 1);
when others =>
C <= B_INPUT;
end case;
end process;
process(SEL_B,C)
begin
case SEL_B is
when "00" => --shift by 0 more
B_OUTPUT <= C;
B_OUTPUT(15 downto 12) <= C(3 downto 0);
when others =>
B_OUTPUT <= C;
end case;
end process;
Debounce Circuit
-- Provides a one-shot pulse from a non-clock input, with reset
-- D_IN: in STD_LOGIC;
-- RESET: in STD_LOGIC;
-- clock: in STD_LOGIC;
-- Q_OUT: out STD_LOGIC);
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal Q1, Q2, Q3 : std_logic;

___________________________________________________________________________VHDL Syntax
--**Insert the following after the 'begin' keyword**
process(clock, RESET)
begin
if (RESET = '1') then
Q1 <= '0';
Q2 <= '0';
Q3 <= '0';
elsif (<clock>'event and <clock> = '1') then
Q1 <= D_IN;
Q2 <= Q1;
Q3 <= Q2;
end if;
end process;
Q_OUT <= Q1 and Q2 and (not Q3);
Multiplexers
2:1
<output> <= <input1> WHEN <selector> ='1' ELSE
<input2>;
4:1
process (<selector>,<input1>,<input2>,<input3>,<input4>)
begin
case <selector> is
when "00" => <output> <= <input1>;
when others => <output> <= <input1>;
end case;
end process;

___________________________________________________________________________VHDL Syntax
8:1
process(<selector>,<input1>,<input2>,<input3>,<input4>,<input5>,<input6>,<input7>,
<in put8>)
begin
case <selector> is
when others => <output> <= <input1>;
end case;
end process;
BLOCK RAM
Dual port
1 clock
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
end if;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
1 clock
process (<clock>)
begin
if (<write_enable> = '1') then
<ram_name>(conv_integer(<write_address>)) <= <input_data>;
<ram_output> <= <ram_name>(conv_integer(<read_address>));
end if;
end if;
end process;
2 clocks
process (<clockA>)
begin
if (<clockA>'event and <clockA> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
end if;
end if;
end if;
end process;
process (<clockB>)
begin
if (<clockB>'event and <clockB> = '1') then
if (<enableB> = '1') then
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
Single Port RAM
process (<clock>)
begin
if (<ram_enable> = '1') then"
<ram_name>(conv_integer(<address>)) <= <input_data>;
else
<ram_output> <= <ram_name>(conv_integer(<address>));
end if;
end if;
end if;
end process;
Read first
process (<clock>)
begin
end if;
end if;
end if;
end process;
write first
process (<clock>)
begin
<ram_output> <= <input_data>;
else
end if;
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
DITRIBUTED RAM
Dual port, Asynch read
process (<clock>)
begin
<ram_name>(conv_integer(<write_address>)) <= <input_data>;
end if;
end if;
end process;
<ram_output> <= <ram_name>(conv_integer(<read_address>));
Single port, Asynch read
process (<clock>)
begin
end if;
end if;
end process;
SHIFT REGISTERS
Dynamic
process (<clock>,<reset>)
begin
<reg_name> <= reg_name((<width>-2) downto 0) & <input>;
end if;
end if;
end process;
<output> <= <reg_name>(<index>);

___________________________________________________________________________VHDL Syntax
PIPO
begin
if <reset> ='1' then
elsif <load_enable> = '1' then
<reg_name> <= <input>;
elsif <clock>'event and <clock>='1' then
<reg_name> <= reg_name((<width>-2) downto 0) & '0';
end if;
end if;
<output> <= <reg_name>;
end process;
PISO
begin
elsif <load_enable> = '1' then
<reg_name> <= <input>;
<reg_name> <= reg_name((<width>-2) downto 0) & '0';
end if;
end if;
<output> <= <reg_name>(<width> - 1);
end process;
SIPO
begin
end if;
end if;
<output> <= <reg_name>;
end process;

___________________________________________________________________________VHDL Syntax
SISO
begin
end if;
end if;
<output> <= <reg_name>(<width> - 1);
end process;
CASE STATEMENT
case (<2-bit select>) is
when "000" =>
<statement>;
when "001" =>
<statement>;
when "010" =>
<statement>;
when others =>
<statement>;
end case;
IF-ELSIF-ELSE
if <condition> then
<statement>
elsif <condition> then
<statement>
else
<statement>
end if;
WITH _____ SELECT
with <choice_expression> select
<name> <= <expression> when <choices>,
<expression> when <choices>,
<expression> when others;

___________________________________________________________________________VHDL Syntax
WHEN _ELSE
<name> <= <expression> when <condition> else
<expression> when <condition> else
<expression>;
Generate
Conditional
<LABEL_1>:
if <condition> generate
begin
<statement>;
end generate;
Multiple
<LABEL_1>:
for <name> in <lower_limit> to <upper_limit> generate
begin
<statement>;
<statement>;
end generate;
LOOP
For Loop
for <name> in <lower_limit> to <upper_limit> loop
<statement>;
<statement>;
end loop;
While Loop
while <condition> loop
<statement>;
<statement>;
end loop;
Process
Combinatorial
process (<all_input_signals_seperated_by_commas>)
begin
<statements>;
end process;

___________________________________________________________________________VHDL Syntax
process (<clock>,<async_reset>)
begin
if <async_reset> = '1' then
<statements>;
if <sync_reset> = '1' then
<statements>;
else
<statements>;
end if;
end if;
end process;
process (<clock>,<async_reset>)
begin
if <async_reset> = '0' then
<statements>;
if <sync_reset> = '0' then
<statements>;
else
<statements>;
end if;
end if;
end process;
begin
if <reset> = '1' then
<statements>;
<statements>;
end if;
end process;

___________________________________________________________________________VHDL Syntax
begin
<statements>;
<statements>;
end if;
end if;
end process;
begin
<statements>;
<statements>;
end if;
end process;
begin
<statements>;
<statements>;
end if;
end if;
end process;
process (<clock>)
begin
if (<clock>'event and <clock> = '1'>) then
<statements>;
else
<statements>;
end if;
end if;
end process;

___________________________________________________________________________VHDL Syntax
process (<clock>)
begin
if (<clock>'event and <clock> = '1'>) then
<statements>;
else
<statements>;
end if;
end if;
end process;
Constant Declaration
constant <name>: <type> := <value>;
Signal Dec
signal <name>: <type> := <value>;
Signal Dec Multiple
signal <name>: std_logic:= '0';
signal <name>: std_logic_vector(15 downto 0):= x"0000";
signal <name>: std_logic_vector(1 downto 0):= "00";
signal <name>: std_logic_vector(31 downto 0):= x"00000000";
Variable Dec
variable <name>: <type> := <value>;
Variable Dec Multiple
variable <name>: std_logic:= '0';
variable <name>: std_logic_vector(15 downto 0):= x"0000";
variable <name>: std_logic_vector(1 downto 0):= "00";
variable <name>: std_logic_vector(31 downto 0):= x"00000000";

___________________________________________________________________________VHDL Syntax
Mealy State Machine
-- This is a sample state machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
--Insert the following in the architecture before the begin keyword
--Use descriptive names for the states, like st1_reset, st2_search
type state_type is (st1_<name_state>, st2_<name_state>, ...);
signal state, next_state : state_type;
--Declare internal signals for all outputs of the state machine
signal <output>_i : std_logic; -- example output signal
--other outputs
--Insert the following in the architecture after the begin keyword
SYNC_PROC: process (CLOCK, RESET)
begin
if (<reset>='1') then
state <= st1_<name_state>;
<output> <= '0';
-- assign other outputs to reset value
state <= next_state;
<output> <= <output>_i;
-- assign other outputs to internal signals
end if;
end process;
--MEALY State Machine - Outputs based on state and inputs
OUTPUT_DECODE: process (state, <input1>, <input2>, ...)
begin
--insert statements to decode internal output signals
--below is simple example
if (state = st3_<name> and <input1> = '1') then
<output>_i <= '1';
else
<output>_i <= '0';
end if;
end process;

___________________________________________________________________________VHDL Syntax
NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
--insert statements to decode next_state
--below is a simple example
case (state) is
when st1_<name> =>
if <input_1> = '1' then
next_state <= st2_<name>;
end if;
when st2_<name> =>
end if;
when st3_<name> =>
when others =>
end case;
end process;
Moore State Machine
-- This is a sample state machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
--Insert the following in the architecture before the begin keyword
--Use descriptive names for the states, like st1_reset, st2_search
type state_type is (st1_<name_state>, st2_<name_state>, ...);
signal state, next_state : state_type;
--Declare internal signals for all outputs of the state machine
signal <output>_i : std_logic; -- example output signal
--other outputs
--Insert the following in the architecture after the begin keyword
SYNC_PROC: process (CLOCK, RESET)
begin
if (<reset>='1') then
state <= st1_<name_state>;
<output> <= '0';

___________________________________________________________________________VHDL Syntax
-- assign other outputs to reset value
state <= next_state;
<output> <= <output>_i;
-- assign other outputs to internal signals
end if;
end process;
--MOORE State Machine - Outputs based on state only
OUTPUT_DECODE: process (state)
begin
--insert statements to decode internal output signals
--below is simple example
if state = st3_<name> then
<output>_i <= '1';
else
<output>_i <= '0';
end if;
end process;
NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
--insert statements to decode next_state
--below is a simple example
case (state) is
when st1_<name> =>
end if;
when st2_<name> =>
end if;
when st3_<name> =>
when others =>
end case;
end process;

VHDL Coding Syntax

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