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[None][fix] Use safeInitRowMax instead of fp32_lowest to avoid NaN #7087
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📝 WalkthroughWalkthroughReplaced multiple initializations of accumulator/max-tracking sentinels from mha::numeric_limits::lowest() to safeInitRowMax across shared memory setup and masking paths. Updated a column bit-mask check from shift-and-test to (mask & (1ULL << col)) form. No interface or structural changes. Changes
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Actionable comments posted: 1
🧹 Nitpick comments (1)
cpp/kernels/xqa/mha_sm90.cu (1)
2381-2387: Bit-mask check rewritten to (mask & (1ULL << col)) == 0: clearer and type-safeThe new form is equivalent to the old shift-and-test but easier to read and avoids precedence pitfalls. Using 1ULL ensures 64-bit shifting; col < 64 here, so no UB.
Optional: For consistency, consider using the same style wherever bit checks appear in this file (some places still use shift forms).
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🔇 Additional comments (4)
cpp/kernels/xqa/mha_sm90.cu (4)
1948-1963: Masking to safeInitRowMax under SPEC_DEC prevents NaNs on fully-masked rowsUpdating masked-out elements to safeInitRowMax here avoids -inf - (-inf) during the max-subtraction softmax step. This is in line with the PR description.
One potential behavioral nuance: if an entire column (or the covered subset) is masked, max equals the sentinel and exp2f(elem - max) yields 1, not 0. Upstream consumers may then see non-zero sums. If downstream expects zero contribution for fully-masked columns, consider a follow-up guard (e.g., treat columns with colMax == safeInitRowMax as zero-sum) or confirm that attention sinks/normalization logic accounts for this edge case in your workloads. Do you want me to draft an optional guard pattern for this degenerate case?
2069-2095: Row-range masking to safeInitRowMax (SWAP_AB path) is consistent and safeUsing safeInitRowMax for rows outside the valid range avoids NaNs in softmax and aligns with the change elsewhere.
2383-2386: Masking to safeInitRowMax under SPEC_DEC non-row path maintains NaN-avoidanceSetting masked elements to safeInitRowMax complements the bit-mask check and avoids -inf arithmetic during softmax.
2393-2418: Non-SPEC_DEC col-range masking switched to safeInitRowMax: consistent with sentinel strategyThe change mirrors other paths and should prevent NaNs if an entire column is masked.
Same note as above: in fully-masked cases, softmax of uniform sentinels produces uniform weights after max subtraction. If zero contribution is desired for fully-masked columns, consider a follow-up guard. I can propose a minimal patch if that’s a requirement.
… some cases Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com>
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PR_Github #15903 [ run ] triggered by Bot |
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PR_Github #15903 [ run ] completed with state |
…#7087) Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com> Signed-off-by: Yuxin <yuxinz@nvidia.com>
…#7087) Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com>
…VIDIA#6282 NVIDIA#6279 * [None][infra] Pin the version for triton to 3.3.1 (NVIDIA#6508) Signed-off-by: qqiao <qqiao@nvidia.com> * [None][infra] Pin the version for triton to 3.3.1 (NVIDIA#6508) (NVIDIA#6519) (NVIDIA#6549) Signed-off-by: Yanchao Lu <yanchaol@nvidia.com> * [fix]: use safeInitRowMax instead of fp32_lowest to avoid NaN (NVIDIA#7087) Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com> * [None][fix] Fix a numerical stability issue for XQA with spec dec Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com> * fix typo Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com> * fix precompiled multi_query_token kernel not having is_fp8_out hash key (NVIDIA#6279) Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com> * [fix] Fix missing fields in xqa kernel cache key (NVIDIA#6282) Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com> --------- Signed-off-by: qqiao <qqiao@nvidia.com> Signed-off-by: Yanchao Lu <yanchaol@nvidia.com> Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com> Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com> Co-authored-by: Emma Qiao <qqiao@nvidia.com> Co-authored-by: Yanchao Lu <yanchaol@nvidia.com> Co-authored-by: Yao Yao <lowsfer@users.noreply.github.com>
In some special cases when all BMM1 result is masked out, we may get NaN due to math with fp32 lowest. Use a larger value to avoid that.
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