MOSFET Biasing Circuit for Analog Amplifiers
Sunday, March 25, 2012 1:19 PM
Vxy = Vx - Vy e.g. VGS = VG - VS VDS = VD - VS VSB = VS - VB
Gate overdrive in MOSFET is written as VGT
VGT = VGS - VT for both NMOS and PMOS VGS = VGT + VT for both NMOS and PMOS For NMOS, VGT > 0 enables current flow, VGT <0 cuts IDS off For PMOS, VGT < 0 enables current flow, VGT > 0 cuts ISD off
In VGT = VGS - VT, "T" is not a circuit node or transistor terminal name Typically VGS is solved in textbooks, I personally prefer to use VGT as solution variable over VGS for a few reasons:
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for biasing analysis, VGT has to be such that it turns the device ON (meaning taking positive value for NMOS, and negative value for PMOS), in solving quadratic equations, we will simply pick the physically meaningful sign that turns on the transistor (VGT >0 for NMOS, and VGT <0 for PMOS) Quadratic equation is easier to formulate and solve - you will see this later on You always need to calculate VGT anyway after solving VGS (if you choose to do so), to check whether your assumption of saturation region operation is correct or not.
Biasing means setting up a desired VGS, VDS, VSB and IDS For a given circuit, with given power supplies, we need to figure out the electrical status of the MOSFET (VGS, VDS, VSB, and IDS) Often as first step we neglect VSB effect (that is body effect), so the primary biasing info is (VGS, VDS, and IDS) if we know (VDS, IDS) and the operating region, we can infer VGS. In any event, we really need to know all of them. We may specify (IDS, VDS) and operating region. One set of biasing info is called a Q-point. Q: quiescent biasing point (essentially DC bias point analysis in SPICE)
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Digital Logic versus Analog Amplification Bias Points Digital logic: (extreme VGS and VDS) Analog: "middle" VGS and VDS
for digital, transistor is set to be either ON (High VGS) or OFF (below VT) for analog amplifiers, a small signal vgs is added on top of the dc biasing point, causing ids to vary, varying ids leads to varying vds. With proper design, the ac vds can be much larger than the ac vgs - giving us amplification
example: weak radio signals from air get amplified - enough amplification of audio signal enables us to hear it
Voltage Transfer Characteristics (VTC) and Load Line Point of View for amplifiers, the dc bias point is chosen to maximize voltage gain
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chosen to maximize voltage gain (sometimes power gain depending on application) - slope of VTC
Bias point analysis is typically for analog, where MOS transistor is typically biased into saturation for amplification - the reason can be easily understood from small signal analysis (later in the analog class) - an output impedance issue
Bias Analysis Approach
Assume an operation region (generally the saturation region for analog - assuming lambda= 0 first) Use circuit analysis to find VGS Use VGS to calculate IDS, and IDS to find VDS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE :An enhancement-mode device with VDS = VGS is always in saturation - gate tied to drain Four-Resistor and Two-Resistor Biasing
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1. Provide excellent bias for transistors in discrete circuits. 2. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. 3. Use single voltage source to supply both gatebias voltage and drain current. 4. Generally used to bias transistors in saturation region. 5. Two-resistor biasing uses lesser components that four-resistor biasing and also isolates drain and gate terminals 6. In IC design, we will use current mirror for biasing
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Constant VGS Biasing Circuit
Monday, March 26, 2012 10:12 AM
Constant VGS Biasing Circuit
A 2-Resistor (2R) voltage divider sets VGS Typically another drain resistor sets VDS for saturation operation always need to check
Constant VGS Circuit Analysis Example:
1. Assume saturation 2. Find IDS, then find VDS, check assumption 3. Run Spice for verification
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Solution:
Constant VGS Circuit Sensitivity What will IDS be if VDD increases to 20V for the same circuit?
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4-Resistor Biasing Circuit
Monday, March 26, 2012 10:17 AM
4-Resistor Biasing Circuit Two resistors RS and RD used
Much more stable than constant VGS circuit due to negative feedback resistor RS
4-R Biasing Circuit Analysis Example: 1. Assume saturation 2. Find IDS, then find VDS, check assumption For the circuit below, find its DC Q-point. First, we can find the gate voltage - what is the VG? And what can we do with it towards finding IDS (via VGT)?
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Once VG is known, we can form an equation about VGT
Solution:
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Simulation Verification Using Multisim Let us put Multisim into work and find out if our manual calculation (34.4uA IDS) is correct or not indeed, the simulated value of IDS is 34.4uA, confirming our hand analysis result
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VDS and VGS are also quite close to calculation Summary of key 4R MOSFET Biasing Circuit Equations:
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Gate Voltage Divider Design gate voltage divider only needs to set the gate voltage, so the current through R1 and R2 should be minimized as it does not contribute to transistor operation A rule of thumb is R1+R2 is usually chosen to limit their current to no more than a few percent of the value of the drain current - as we will show below, you may have other considerations too. In our example, I2 = 10V/(1Mohm + 1.5Mohm) = 4uA
4-R Bias Circuit Design Example 1 (available in our text) For the same R2, R1 as in previous circuit, redesign the Rs and Rd values to set IDS=100uA, VDS=6V Approach: 1. using VGT as variable,
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1. 2. 3. 4. 5.
using VGT as variable, make saturation assumption, solve VGT then VGS Solve Vs, Rs Solve Vd, Rd
IDS=100uA, VDS=6V
Solution:
using VGT as variable, make saturation assumption, solve VGT then VGS
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Solve Vs, Rs
Solve Vd, Rd
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let us run this in Multisim and see if our design is correct or not, below is the result you see Multisim shows our design gives 100uA IDS,
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The gate network design often also involves a specification of the Thevenin equivalent source resistance defined as follows:
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MOS 4R Design Example 2:
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Problem analysis:
Approach: assume saturation, find VGT,
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then find VGS,
then assume a good value of VS to find VG, determine R1 and R2
Solution:
Choose V(Rs)=3V, V(RD)=3V.
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now let us verify our design using Multisim
Simulation shows our design is correct.
Vdd sensitivity for 4-R circuit with different Rs values.
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Vdd sensitivity for 4-R circuit with different Rs values. Let us define a MOSFET, and then construct a 4R circuit:
m1 = Mosfet(vt=1,
kn=25e-6)
circuit1 = Mos4rCircuit(r1=1e6,
r2=1.5e6, rs=39e3, rd=75e3, mosfet=m1, vdd=10)
## now let us look at the impact of Rs on Vdd sensitivity of bias point for rs in array([10e3, 39e3]):
rs_kilo = float(rs) / 1000 print "rs = %6.4f kohms" % (rs_kilo) for vdd in linspace(10, 14, 5): print "vdd = ", vdd qpoint = circuit1.update_value(vdd=vdd, rs=rs) ## print circuit1 print qpoint print '\n'
The following is the output of the program:
You can see clearly the 39kohm Rs circuit bias point changes much less. rs = 10.0000 kohms vdd = 10.0 Vds = 4.26 V ids = 67.54 uA rs = 39.0000 kohms vdd = 10.0 Vds = 6.08 V ids = 34.39 uA
vdd = 11.0 Vds = 3.97 V ids = 82.73 uA
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vdd = 11.0 Vds = 6.34 V ids = 40.84 uA
vdd = 11.0 Vds = 3.97 V ids = 82.73 uA
vdd = 11.0 Vds = 6.34 V ids = 40.84 uA
vdd = 12.0 Vds = 3.60 V ids = 98.82 uA
vdd = 12.0 Vds = 6.59 V ids = 47.47 uA
vdd = 13.0 Vds = 3.16 V ids = 115.73 uA
vdd = 13.0 Vds = 6.81 V ids = 54.27 uA
vdd = 14.0 vds= 2.66406722359 V is less than Vgt = 3.26636084983 V Saturation assumption invalid! solution not meaningful Vds = 2.66 V ids = 133.36 uA
vdd = 14.0 Vds = 7.02 V ids = 61.21 uA
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Homework on 4R MOS biasing circuits, Due Friday, July 13
Sunday, March 25, 2012 2:09 PM
1. (a) Problem 4.97 (a). Your transistor parameters should come from Table 4.6 (30). (b) Verify your analysis using Multisim (20).
2. (a) Problem 4.105. Hint: you are not given the transistor Kn. Rather only KP parameter (K_n' in our text) is given. So you as the designer are responsible for determining W/L (30). (b) Verify your design using Multisim (20).
Hints:
For design problem, your answer is not unique. Here we are given K', but not K. That means the transistor K, is a design decision we have to make, via the choice of transistor size W/L. We need to choose VGT.
Once VGT is chosen, as IDS is given, we know K, then using K', we can determine W/L. We do not want VGS to be too close to threshold (i.e. VGT too close to 0V). Choosing VGT>1V is common for
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VGT too close to 0V). Choosing VGT>1V is common for discrete designs..
Too high a VGT makes it hard to work in saturation region. It has to be less than VDS by a good margin!
Also consider output voltage swing, to first order, we can make Vgt=Vds/2 (ideal linear transistor with no knee).
it is not a good idea to choose W/L, because it may lead to a bad VGT, e.g. VGT=0.1V or VGT > VDS (linear)
we want to have negative feedback to stabilize the circuit. So we do not want to choose too small V_{RS}. We have in total 9V - Vds (3V) = 6 V to work with between V_{RS} and V_{RD}. Here we could choose V_{RS}=3V, V_{RD}=3V to have reasonable feedback and swing.
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MOS Transistor Amplifier Operation Principle
Wednesday, March 28, 2012 11:13 AM
So far, we have just been given a magical (IDS, VDS) pair, how should we decide their values? That is, how should the DC bias point be chosen? Let us for now just consider adding a small ac input Vin on top of a dc VGS (Vgs,dc in the illustration below):
A change in Vgs causes a change in IDS, which then causes a change in the output voltage. So first order theory gives us Voltage gain is thus:
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Voltage gain is thus:
is called the transconductance gm, which we can easily evaluate from either first order model or measurement. This equation, however, assumes very small AC input voltage, so that the output voltage change is still small. So if we make the small signal voltage gain 100, and we set the AC input voltage amplitude to 1mV, then the AC output voltage amplitude will be 100 * 1mV = 0.1V.
However, if I make the ac input amplitude 1V, will the ac output amplitude be 100 V? why?
Large Signal Votlage Swings: When
is below threshold, the transistor cuts off. Thus, the highest
possible is . When
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When
is very high, the current will increase, and hence pull down . For an ideal transistor with an ideal knee voltage or with a drain saturation voltage , the best
low we can achieve occurs when , and decreases to zero. If we further assume that the transistor is linear, we find that a maximum output voltage swing of / 2 can be obtained if we choose a DC equal to , as shown below:
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Often we have a source feedback resistor for stable dc bias point, which will of course reduce the amount of current modulation we can have for a given gate voltage change.
This is often not desired as it will reduce voltage gain. We can use a large bypass capacitor in parallel with the source resistor, so that the ac signals will not go through Rs. We then need to change our analysis slightly:
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The load resistance can be immediately determined from the above illustration, can you write down an expression of Rload in terms of the IDS, VDS, and VS dc values?
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Adding AC input and Taking AC output
Wednesday, March 28, 2012 11:03 AM
Capacitors can be used to block DC but pass AC signals So in practice, the 4R amplifier circuit using 4R bias configuration looks like
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Experimental 4R MOS amplifier
Tuesday, March 27, 2012 5:59 PM
This is the schematic in our lab manual I used a different design this time, same transistor, different R's,
Now try increasing the input amplitude, you will see distortion. Why? When input positive peak is too high, the max IC is limited by VDD (when VDS is close to zero), so Vout value will bottom out a
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VDD (when VDS is close to zero), so Vout value will bottom out a bit above Vs - the feedback voltage we set. When input negative peak value is too low, IC is too small (say zero), there will be no voltage drop across collector resistor, collector voltage will max out at VDD. You can of course also look at spectrum analysis, better use scope channel, rather than AI: Put waveform, spectrum together, note the small level of distortion
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Next, we increase input amplitude Look at how much more THD we have! You can examine the waveform for this high input amplitude:
Now let us make the input amplitude even higher, so that we can see the drain current reaching its both extremes:
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15V is the VDD used, So you see the high of the drain voltage (which has both dc and ac components) is VDD, the low of the drain voltage is the DC VS value, as the source is essentially at ac ground (meaning voltage is not changing over time, or it has no ac component)
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4R NPN Circuit
Tuesday, March 27, 2012 4:48 PM
Bipolar Transistor and Circuits
- Review of PN junction / diode operation - Minority carrier injection and diffusion - Re-inventing NPN bipolar transistor - Normal operation mode - Circuit model, IS, and Beta - Simulating bipolar in SPICE - 4-R bias circuit using bipolar - Other possible operation modes (less use in modern days) - the PNP transistor
Consider a NPN structure.
Let us forward bias the first junction, i.e. VBE >0 reverse bias the second junction, i.e. VCB > 0
Electron diffusion current will be pulled by the strong e-field in the 2nd junction, as electrons move against e-field, thus the electrons injected from the first pn junction will be collected by the 2nd Nregion - called collector The first n-region is called emitter, as it emits electrons
the P-region is called base for historical reasons (dates back to the invention of transistor)
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4R NPN analysis
Tuesday, March 27, 2012 4:53 PM
Simplified Model for Forward Mode
Current in base-emitter diode is amplified by commonemitter current gain bF and appears at collector; base and collector currents are exponentially related to baseemitter voltage.
Further approximation for hand analysis:
Base-emitter diode is approximated by constant voltage (VBE = 0.7 V for Si at 300K) You should then never calculate IC using IS * exp(0.7/VT) - as VBE=0.7 is an approximation that works only when voltage is calculated Your IC is exponentially sensitive to VBE! The constant VBE approximation allows us to simplify the process of determining IC or IB from voltage loops - as illustrated below
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Relations Between IB, IE and IC in Forward Mode
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Example of 4R Bipolar biasing analysis:
Problem: for a forward beta (beta_F) of 75, find bias point (IC, VCE) for the 4R bias circuit
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Solution Procedures:
Solution: 1) find the equivalent voltage and resistance (VEQ and REQ) of base bias network (R1 and R2) 2) from input voltage loop, find IB and IC
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2) from input voltage loop, find IB and IC 3) from output voltage loop, find VCE
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4R NPN Design
Tuesday, March 27, 2012 5:01 PM
We want the current of base voltage divider network (R1 and R2) much smaller than IC to save power, a good choice is that I2 (or I1) < IC/5 We want VEQ to be large enough that small variations in the approximated value of VBE = 0.7V wont affect IE. We want base voltage (VB) to be set by R1 and R2, and not affected much by IB - as transistor beta has a large variation in manufacturing. That is, I2 = I1 + Ib, but Ib << I1, or I2 (or I1) > 10 IB
Four-Resistor Bias Network for BJT: Design Procedures
Select VE from VCE requirement and VCC, the key is we need to partition (VCC-VCE) between RE and RC. Do not make VE too small (0.7V will be too small) RE is determined by the VE chosen and desired IC. IE=(beta+1)IB = (beta+1) * IC / beta. RE = VE/IE. RC is determined as RC = (VCC - VCE - VE) / IC. Determine VB from VB = VBE + VE, and VBE is approximately 0.7V Select R1 to set I1 = 9IB. Determine R1 = VB / I1. Select R2 to set I2 = 10IB. Determine R2 = (VCC - VB) / I2
Design Example: Four-R Bias Network Problem: Design 4-resistor bias circuit with given parameters. Given data: IC = 750 uA, bF = 100, VCC = 15 V, VCE = 5 V
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Given data: IC = 750 uA, bF = 100, VCC = 15 V, VCE = 5 V Assumptions: Forward-active operation region, VBE = 0.7 V Analysis: Divide (VCC - VCE) equally between RE and RC. Thus, VE = 5 V and VC = 10 V
Solution:
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SPICE result is very close to our design target IC = 748.8 uA (our design goal is 750uA)
A better way of design Utilizing transistor IS
We can improve design accuracy by using a more exact way of calculating VBE
Recall IC = IS * exp (VBE/Vt) Consider using a transistor with IS = 1e-15A, BF=100 for
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Consider using a transistor with IS = 1e-15A, BF=100 for the same design:
VBE = Vt * ln(IC/IS) = 0.025*ln(750e-6/1e-15) = 0.6836V
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PNP Transistor
Tuesday, March 27, 2012 5:10 PM
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PNP 4R Design
Tuesday, March 27, 2012 5:11 PM
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Symmetry between NPN and PNP designs
Tuesday, March 27, 2012 5:12 PM
The NPN and PNP circuits are very much alike. If you examine the NPN and PNP 4-R biasing circuits, you will find symmetry. So you can take a NPN design and convert it into a PNP design in a minute.
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Homework on bipolar 4R, due TBD
Friday, March 30, 2012 9:14 AM
Use IS=10-15A, BF=100, BR=5 for all problems below for both hand calculation and simulation. You are asked to calculate VBE / VEB using the IS given. VBE = 0.0258*ln(IC/IS) for NPN, and VEB = 0.0258*ln(IC/IS) for PNP. So do NOT make the 0.7V assumption. 1. Problem 5.91 (a) only (25) 2. Problem 5.93 (a) only. There is a typo, V_E should be V_{RE} (25) 3. Verify your bias points obtained above using Multisim, show schematic, edit model screen, and bias point display (30) 4. (20 points) Play with the bipolar transistor 4R amplifier provided below in Multisim. Set FGEN frequency to 5 or 10 kHz to begin with. Show waveforms of AC input, AC output, base, and collector voltage for Vin=0.02V. Then increase Vin until you see collector voltage clips at both the high and low ends. For a 4 channel scope you can only probe 4 signals at one time. You can use another scope with more channels so you can simultaneously measure more signals (e.g. including emitter voltage waveform too). You can also choose sine, triangle and square wave inputs if you are using ELVIS FGEN as your source input.
The multisim version in the pc labs may not be the latest. If it is, you can drag the picture below to a blank design schematic and then start using it.
It is pretty straightforward to create the schematic yourself, use the 2N3904 bipolar transistor, which is what you use in the lab for amplifiers.
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Experimental 4R Amplifiers
Tuesday, March 27, 2012 5:57 PM
We will build and test 4R amplifiers in the lab.
Here is measurement on a similar but slightly different amplifier
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dB definitions for voltage, current and power gain
Monday, April 02, 2012 2:27 PM
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