COM 353 Microprocessors

Lecture 3

Prof. Dr. Halk Gmkaya

haluk.gumuskaya@gediz.edu.tr haluk@gumuskaya.com http://www.gumuskaya.com

Introduction to 8-bit Microprocessor Architecture and Operation

Computer Engineering Department

Tuesday, October 23, 2012

A Microprocessor Based System 1. Basic Microprocessor System Concepts

2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255

I
SSTEM YOLU
8255, 8256 8253 (8254) 8251 8257 8259 8279, ...

ROM

RWM

Giri
(Temel) 3-durumlu buffer

k
(Temel) Latch, FF

Programlanabilir Giri/k Birimleri

A collection of addressable registers: Those registers reside within the microprocessor are internal registers, and those exist in the ROM, RWM, and I/O ports are external registers.

Typical Partial Set of System Bus Signals

Name A31A0 D63D0 RD WR IO/M MEMR MEMW IOR IOW RESET Function Address bus Data bus Generalized read strobe Generalized write strobe Status (I/O or memory reference) Memory read strobe Memory write strobe Input device read strobe Output device write strobe System reset out Number 16, 20, 24, 32, 36 8, 16, 32, 64 1 1 1 1 1 1 1 1 Direction* Output Bidirectional Output Output Output Output Output Output Output Output

3 Buses of a P-Based System

Mikroilemcili Sistem

CPU Saklayclar

ip-zeri yollar

Yerel Sistem Yolu

ALU

Hafza

I/O

I/O

* Direction is specified with respect to the microprocessor.

Harici Sistem Yolu

Simple Input Port for a P-Based System

Giri Port'u
Sistem Veri Yolu

Simple Output Port for a P-Based System

k Port'u
Sistem Veri Yolu

Giri Cihaz

Latch E

3-Durumlu Buffer

D0 D1 Dm
Giri Cihaz Seme Darbesi

k Cihaz

Latch

D0 D1 Dm
k Cihaz Seme Darbesi

Veri Tutturma Darbesi Cihaz Seme Lojii

A0 A1 An

Cihaz Seme Lojii

A0 A1 An

IO / M RD

IO / M WR

Internal Architecture
1. Basic Microprocessor System Concepts

2. Microprocessor Architecture and Operation

3. Intel 8085 Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255
zel Amal Saklayclar Genel Amal Saklayclar

R0 R1 R2 R3

ALU
(Arithmetic Logic Unit)

1. Control Unit 2. General Purpose Registers 3. Special Purpose Registers

R3 SR (Status Register) IR (Instruction Register) IP (Instruction Pointer) SP (Stack Pointer) MAR (Memory Address Register) MBR (Memory Buffer Register) (FPU, hafza ynetim birimi, cache, ...) Teknolojinin gelimesiyle eklenen dier donanm ve yazlm

Kontrol Birimi

4. Arithmetic Logic Unit 5. Other Special Units

1. Control Unit
Harici Veri Yolu MBR

Simplified States of Control Unit

Komut mikroilemcide Komut Okuma (Fetch)

It controls and synchronizes all data transfers and transformations in the microprocessor system.
Dahili Veri Yolu

Komut Saklaycs

IR

Yrtme (Execute)

Komut Kod zc

Kontrol Birimi Saat

Dahili Saklayclara Kontrol Sinyalleri Bayraklar

The output of the IR is decoded and used by the control unit to develop a sequence of microoperations (microistructions) and register transfers that execute the instruction.

Komut yrtmesi biter

RESET

Durma (HALT) Komutu Durma (Halt)

Donanm sfrlamas olmad srece dur RESET

Harici Kontrol Girileri

Harici Kontrol klar

Fetch Decode Execute Cycles

Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

2. General Purpose Registers

A (ACC) They are used for storage, arithmetic and logic operations (x86), and addressing purposes.

Read an instruction from memory

Determine required operations

Intel 8085 registers

The registers are used and operated upon either singly or in pairs

Locate and obtain operand data Compute result value or status Write results to memory for later use

X86 registers

Determine next instruction

3. Special Purpose Registers

F (Flags) (8-bit status register, modified after an ALU operation) PC (Program Counter points to the next instruction to be executed in memory) MAR (Memory Address Register) 8085 registers MBR (Memory Buffer Register) SP (Stack Pointer)
A

4. Arithmetic Logic Unit

AX BX CX DX DI SI

Temp. Reg

BP SP

X86 registers
Internal Bus

ALU

ALU

Flags
Flags

8-bit ALU (8085)

16-bit ALU (8086/8088)

Arithmetic and logic operations on one or two 8-bit, 16-bit (x86), and 32-bit (x86) operands are performed in this unit.
Halk Gmkaya

5. Other Special Units

External Architecture

FPU (Floating Point Unit) Cache Memory Memory Management Unit .

Address Bus Data Bus Control Bus 1. Bus control 2. Bus status 3. Interrupts 4. Bus arbitration 5. Coprocessor signaling 6. Misc

The pins on a CPU chip

Control Bus

Address Bus: Common address bus widths are 16, 20, 32, and 64 Data Bus: Common widths are 8, 16, 32, and 64. Control Bus: The control pins regulate the flow and timing of data to and from the CPU and have other miscellaneous uses. Control pins can be roughly grouped into the following major categories: Bus Control Interrupts Bus Arbitration Coprocessor Signalling Status Miscellaneous

Bus Control: Mostly outputs from the CPU to the bus telling whether the CPU wants to read or write memory or do something else. The CPU uses these pins to control the rest of the system. Status: They show the status (i.e. bus operation, MEMR, IOW) of CPU. Interrupts: They are inputs from I/O devices to the CPU. Bus Arbitration: These pins regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time. Coprocessor Signalling: Some CPU chips are designed to operate with coprocessors such as floating point chips, graphics or other chips. Miscellaneous: CLK, XTAL, reset, power,

Internal Architecture of 8085A

1. Basic Microprocessor System Concepts
2. Microprocessor Architecture and Operation
INTA INTR RST5.5 RST6.5 RST7.5 TRAP SID SOD Kesme Kontrol Seri I/O Kontrol

3. Intel 8085 Microprocessor

4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255
Bayraklar (F) X1 X2 CLK OUT READY CLK retimi Kontrol A Geici Reg. IR B D H SP PC C E L

ALU

Komut Kod zc

Zamanlama ve Kontrol
Durum DMA RESET MAR MAR / MBR

RD WR ALE

S0 S1 IO/M HOLD HLDA RIN ROUT

A15- A8 Adres Yolu

AD7- AD0 Adres/Veri Yolu

External Architecture of 8085A

X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 Vcc HOLD HLDA CLK (OUT) RESET IN READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8 Adres Yolu A15 - A0 Veri Yolu D 7 - D0 Yol Kontrol ALE RD WR READY INTA Yol Durum IO/M S0 S1 HOLD HLDA Yol Hakemlii
8 16

Multiplexing of Address/Data Pins of 8085A

8085A
Kesmeler

TRAP RST 7.5 RST 6.5 RST 5.5 INTR

A15 - A8
74LS373

A15 - A8

Adres Yolu A15 - A0

8085A

32 31 30 29 28 27 26 25 24 23 22 21

8085A

AD7 - AD0
C OE

A7 - A0 Adres Latch' D7 - D 0 Veri Yolu

SID SOD RESET IN RESET OUT CLK X1 X2 eitli

ALE

(a)

(b)

8085A Based System

Machine Cycles and Timing

Machine cycle: The fetching and execution of a single instruction. It consists of one more read/write operations (references) to memory or an I/O device.

There are 7 different types of machine cycles in the 8085: Opcode fetch Memory read MEMR Memory write MEMW I/O Read IOR I/O Write IOW Interrupt acknowledge Bus idle

Machine Cycle and State Information for the 8085A

The Format of 8085 Instructions and Instruction Fetch Cycle

The instructions consist of 1 to 3 bytes. Therefore, instruction fetch is 1 to 3 machine cycles The first machine cycle in an instruction cycle is always an OPCODE FETCH, and the 8-bits obtained during an OPCODE FETCH are always interpreted as the OP code of an instruction. The total number of machine cycles required varies from 1 to 5, with no one instruction cycle containing more than 5 machine cycles.

Opcode Opcode Operand (a) (b) Opcode Operand1 Operand2 (c)

3 status signals generated at the beginning of each machine cycle identify each type and remain valid for the duration of the cycle.

Bus Status Machine Cycle Opcode fetch Memory read Memory write I/O read I/O write Interrupt Ack. Bus idle HLT DAD Ack. of RST, TRAP IO/M 0 0 0 1 1 1 0 1 3-state S1 1 1 0 1 0 1 1 1 0 S0 1 0 1 0 1 1 0 1 0 RD 0 0 1 0 1 1 1 1 3-state

Bus Control WR 1 1 0 1 0 1 1 1 3-state INTA 1 1 1 1 1 0 1 1 1

(a) 1-byte (b) 2-byte (c) 3-byte 8085A instructions.

Execution of STA and LDA Instructions

Timing Values of 8085AH Microprocessor

STA (Store Accumulator Direct) transfers the contents of ACC to an external register (a memory register or a memory mapped output register) whose address is specified in the instruction. The opcode for STA is 32h. This register can be located anywhere in the 64 K memory space that the 8085 can directly address, 16-bits are required for the address. LDA (Load Accumulator Direct) does the reverse operation. It reads from an external register to the ACC. The opcode is 3Ah.

Processor 8085AH-1 8085AH-2 8085AH-1 8085AH-1

Crystal MHz (fc) 11.976 10.000 6.250 6.144

State Time ns (T) 167 200 320 325.5

ADD Instruction (s) 0.6680 0.8000 1.2800 1.3000

ADDR ADDR + 1 ADDR + 2

lem Kodu Dk Adres Yksek Adres

byte 1 byte 2 byte 3 STA veya LDA komutu

3-byte STA and LDA instructions

Execution of STA and LDA Instructions

Activities Associated with the T-States of 8085A

Each machine cycle is divided by system clock into a number of state transitions, or T states, which correspond to the period between two negative going transition of that clock.

T1

A memory or I/O device address is placed on the address/data bus (AD7-AD0) and address bus (A15-A0). An address latch enable, ALE, pulse is generated to facilitate latching the low order address bits on AD7-AD0. Status information is placed on IO/M, S1, and S0 to define the type of machine cycle. The halt flag is check. Ready and hold inputs are sampled. PC is incremented if machine cycle is part of an instruction fetch. In all machine cycles except BUS IDLE, one of the control strobes RD, WR, or INTAmakes a 1 to 0 transition. (optional) This state is entered if the ready line is low. The states of the address, data and control signals remain the same as at the end of T2. An instruction byte or data byte is transfered to/from memory the microprocessor. The active control strobe makes a 0 to 1 transition. The contents of instruction register (IR) are decoded. These states are used to complete the execution of some instructions.

T2

Tw T3 T4 T5 - T6

T-States of LDA and STA Instructions

Execution of IN and OUT Instruction

IN InputPort IN reads the contents of an input device located at InputPort to the accumulator (ACC). The opcode for IN is DBh. InputPort is an 8-bit port address which is an operand in this instruction. 256 input ports are possible with this 8-bit port address. OUT OutputPort OUT does the reverse operation. It writes the contents of the ACC to the output port located at OutputPort. OutputPort is also an 8-bit address. This means 256 possible output ports. The opcode for OUT is D3h.
ADDR ADDR + 1 lem Kodu Port Adresi byte 1 byte 2 IN veya OUT komutu

Machine Cycles 1. Opcode fetch 2. Memory read 3. Memory write 4. Memory write (STA) or read (LDA) Total T-states for 4 machine cycles

T-States 4 3 3 3 13

For STA and LDA instructions, the number of T-states required for the execution is 13. If the 8085 is operating at a 325.5 nS state time, the STA/LDA instruction cycle is executed in 4.23 S.

2-byte IN and OUT instructions

Execution of IN and OUT Instruction

1. Basic Microprocessor System Concepts
2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor

4. 8085 Microprocessor Based System

5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255

System Memory

System Memory Using Full Decoding

D7 - D0 Veri Yolu A11 - A0 A11 - A0 12 D7 - D0

The 8085 system has ROM and RWM memory modules, one input port (a simple 8-bit three-state buffer 74LS244) for reading switches, and one output port (74LS374) for driving a LED display. Use the memory system example given in the first lecture. 4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts.
0000h ROM 0FFFh 1000h 17FFh 1800h 4K
0000h 0FFFh A15 A 12 A11 A8 A7 A4 A3 A0
A13 A12 A11

2732 4K x 8 EPROM CE OE

74LS138 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
07FFh-0000h 0FFFh-0800h 17FFh-1000h

RD

0 0 0 0 0 0 0 0
lk 4K'lk blou seer

0 0 0 0 1 1 1 1

0 0 0 0 1 1 1 1
4K ROM iinde bir hafza hcresini seer

0 0 0 0 1 1 1 1
A15 A14 G2A G2B G1

A10 - A0 11

A11 - A0

D7 - D0

RWM

2K
1000h 17FFh 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1

IO / M

6116 2K x 8 RWM CS OE WE

FFFFh

Bo

0 0 0 0 1 1 1 1
2K RWM iinde bir hafza hcresini seer

0 0 0 0 1 1 1 1

58K
nc 2K'lk blou seer

RD WR

Memory Map

Address Bit Map

A Simple Input Port at F0h (partial decoding)

A Simple Output Port at F1h (partial decoding)

+5V

+5V

D7

74LS244 Octal Buffer

D0
+5V RD IO / M A7 A6 A5 A4

1 1 1 1 1 0 0 0 Anahtar bilgisi F8h

S7

D7

D7
74LS374 Octal FF

D0
+5V WR IO / M A7 A6 A5 A4 A0

D0
CLK OE

OE Cihaz Seme Darbesi F0h Adresindeki Giri Port'u

S0

Cihaz Seme Darbesi F1h Adresindeki k Port'u

Simple System Test Program at ROM

IN CMA STA LDA OUT HLT F0h 1000h 1000h F1h ; F0h adresli giri port'undan oku ((ACC) <- (F0h)). ; Okunan verinin bit'lerini tersle ((ACC) = (ACC)'). ; ACC'yi RAM'n 1000h nolu hcresine yaz. ; RAM'n 1000h nolu hcresinden ACC'ye oku. ; F1h adresli k port'una yaz ((ACC) -> (F1h)). ; Program yrtmesini durdur.

Execution of In F0h Instruction

ADRES
Program Assembly and Machine Code Address 0000 0002 0003 0006 0009 000B Machine Code DB F0 2F 32 00 10 3A 00 10 D3 F1 76 Assembly Code IN CMA STA 1000h LDA 1000h OUT F1h HLT F0h

VER
DBh F0h 2Fh 32h 00h 10h 3Ah 00h 10h D3h F1h 76h

KOMUTLAR IN F0h CMA STA 1000h

0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh

LDA 1000h

OUT F1h HLT

Execution of STA 1000h Instruction

Execution of Program in the 8085 Simulator

Assembly Program and its Machine Code

Registers

EPROM and RWM

Input and Output Ports

Input and Output Address Spaces

1. Basic Microprocessor System Concepts
2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor 4. 8085 Microprocessor Based System
IN PortNumber instruction Read from an input port located at PortNumber to the accumulator (ACC) [PortNumber]. PortNumber = 00h FFh: 256 input ports OUT PortNumber instruction Write the contents of ACC to an output port located at PortNumber. Again 256 output ports. I/O Decoding of Control Lines and Addresses The corresponding IO/M, RD, WR signals are generated when these instructions are executed by the CPU. These signals and some address lines are used by the decoding logic to access the I/O ports.

5. Isolated I/O Using IN and OUT Instructions

6. Memory Mapped I/O 7. Programmable I/O and 8255

I/O Address Spaces and Ports

Since there are 2 different instructions for I/O access, two different address spaces exist for I/O operations. Totally 512 ports (8085)

1. Basic Microprocessor System Concepts

2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions

6. Memory Mapped I/O

7. Programmable I/O and 8255

I/O Devices at Memory Address Space

I/O devices are located at memory address space. Use memory related instructions (like LDA, STA) to access I/O devices. The I/O decoders monitor memory related control lines and addresses.

An Input Device at a Memory Address

To access an input port, use a memory access instruction, like LDA The input decoder monitors memory related control lines and addresses. An example: An input device is located at a memory address F000h. Use partial address decoding, use just 4 address lines from the address bus: A15, A14, A13, and A12.

+5V IO / M RD A15 A14 A13 A12

MEMR

F000h Adresindeki Giri Port'unu Seme Darbesi

An 8-input NAND gate is used as an input decoder. The input device is located at F000h. When IN F000h is executed by CPU, at the last machine cycle, F000h is placed onto the address bus, IO/M becomes 0. Finally RD is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the 3-state buffer of the input device is activated, and data at this device is read to ACC by CPU.

An Output Device at a Memory Address

Memory and I/O Address Spaces

To write to an output port, use a memory access instruction, like STA. The output decoder monitors memory related control lines and addresses. An example: An output device is located at a memory address F001h. Use partial address decoding, use just 5 address lines from the address bus: A15, A14, A13, A12, and A0.
+5V IO / M WR A15 A14 A13 A12 A0 MEMW

F001h Adresindeki k Port'unu Seme Darbesi

An 8-input NAND gate is used as an output decoder. The output device is located at F001h. When OUT F001h is executed by CPU, at the last machine cycle, F001h is placed onto the address bus, IO/M becomes 0. Finally WR is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the input device is activated, and 8-bit data at ACC is written to the output device by CPU.

Why Memory Mapped I/O ?

Some

processors may not have such separate IN and OUT instructions for I/O in their instruction set. Using IN and OUT, you can only read from or write to an I/O device. If you want to do some other operations, like OR, AND, ADD, ) directly on I/O devices, the memory mapped I/O technique can be used. If the number of I/O devices is larger than 512 (for 8085) use the memory mapped I/O.

1. Basic Microprocessor System Concepts

2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O

7. Programmable I/O and 8255

Programmable I/O

8255 IC (a) and Logic Diagram (b)

PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 Veri Yolu

In our previous simple example, we had very simple I/O devices. In general microprocessor based systems, like PCs, have programmable I/O devices. These devices have programmable I/O ports. In addition to simple reading and writing data, they have also some build-in additional features, like timers/counters, interrupts, bit-addressable ports,

D7-D0 PA7-PA0
D0 - D7 PA

Data Bus (bidirectional) Port A Port B Port C Chip Select Port Address Read Control Write Control Reset Input +5 Volt 0 Volt

PB7-PB0 PC7-PC0 CS A0, A1 RD WR RESET VCC GND

8255A

32 31 30 29 28 27 26 25 24 23 22 21

8255A
CS A1 A0 RD WR RESET (b)

PC

Some examples: Basic and handshake parallel I/O (8255, 8256) Timer/counter (8253/8254) Interrupt controller (8259) Serial/parallel data communication (8250, 8251, 8256) 1-bit data I/O (bit addressable) (8256) Keyboard/display interface (8279) Block data transfer between memory and external world (DMA) (8257)

PB

(a)

8255A Chip and Port Select Signals CS 0 0 0 0 1 A1 0 0 1 1 X A1 0 1 0 1 X Selected Port Port A Port B Port C Control Register 8255A not selected

Programmable pripheral device

4 addresses are occupied in I/O space

8255A at C0h and its Select Logic

D7 - D0 D7 - D 0 PA PA = C0h
D7 0/1 D6 D5 D4 D3

8255 Control Word

Kontrol Kelimesi

D2

D2

D0

D7

D6

D5

D4

D3

D2

D1

D0 Grup B Port C (Dk PC 3 - PC0) 1 = Giri 0 = k Port B 1 = Giri 0 = k Mod Seimi 1 = Mod 0 0 = Mod 1 Grup A Port C (Yksek PC 7 - PC4) 1 = Giri 0 = k Port A 1 = Giri 0 = k Mod Seimi 00 = Mode 0 01 = Mod 1 1X = Mod 2 1 = I/O Modu 0 = BSR modu

Kontrol Kelimesi

+5V A7 A6 A5 A4 A3 A2 A1 A0 IOR IOW A1 A0 RD WR CS

BSR Modu (Bit Set/Reset) I / O Modu

PB

PB = C1h

C Port'u zerinde tek bit 0'lama ve 1'leme yaplr A ve B port'lar etkilenmez

Mod 0 A, B ve C port'lar iin basit giri/k

Mod 1 A ve (veya) B port'lar iin el skmal (handshake) alma C port'u el skma sinyalleri iin kullanlr

Mod 2 A port'u iin iki ynl veri yolu Port B: Mod 0 veya 1 de alr C port'unun bit'leri el skma sinyalleri olarak kullanlr

PC

PC = C2h

CS = 0 A7 A6 A5 A4 A3 A2 1 1 0 0 0 0 A1 A0 0 0 0 1 1 0 1 1

Address = = = = C0h C1h C2h C3h

Selected Port PA PB PC Control Register

8255 for the 8085 Based System

Instead

I/O Operations Using 8255

+5V

of using a 3-state buffer and a latch for I/O devices, this time use an 8255 for the 8085 based system example. 8255 base address is F0h, that is the address of PA. PA will be used to read switches. PB (at F1h) will be used to drive the LED display. PC (at F2h) will not be used. Control register is at F3h. Control word = 1 0 0 1 0 0 0 0 = 90h.

8255A Veri Yolu D0 - D7

+5V IO / M A7 A6 A5 A4 1 1 1 1 1 0 0 0 D7 +5V S7

D0 - D7 PA

CS A1 A0 A1 A0

S0

PB
RD WR RD WR RESET D0

PC

A simple I/O example using a 8255 located at F0h. MVI A, 90h OUT F3h IN F0h; OUT F1h ; (ACC) 90h, Load ACC with 90h (A: input, B: output) ; (F3) (ACC), write the contents of ACC (90h) to control register, 8255 is programmed. ; read switches (ACC) (F0h) ; drive LEDs (F1) (ACC)

References

Mikroilemciler ve Bilgisayarlar, 3. Basm, H. Gmkaya, ALFA, 2002. (Chapter 3).