Instruction set of

8086 Microprocessor
By
K. SAI KRISHNA
Assistant Professor
1

Software
The sequence of commands used to tell a microcomputer what to
do is called a program,
Each command in a program is called an instruction
8088 understands and performs operations for 117 basic
instructions
The native language of the IBM PC is the machine language of the
8088
A program written in machine language is referred to as machine
code
In 8088 assembly language, each of the operations is described by
alphanumeric symbols instead of 0-1s.

ADD AX, BX
(Opcode)

(Destination operand)

(Source operand )
2

Instructions
LABEL: INSTRUCTION
Address identifier

Ex.

START: MOV AX, BX

; COMMENT
Does not generate any machine code

; copy BX into AX

There is a one-to-one relationship between assembly and

machine language instructions
A compiled machine code implementation of a program
written in a high-level language results in inefficient code
More machine language instructions than an assembled version of an
equivalent handwritten assembly language program

 Two key benefits of assembly language

programming
It takes up less memory
It executes much faster

Applications
One of the most beneficial uses of
assembly language programming is
real-time applications.
Real time means the task required by the
application must be completed before any other
input to the program that will alter its operation can
occur
For example the device service routine which
controls the operation of the floppy disk drive is a
good example that is usually written in assembly
language
5

 Assembly language not only good for

controlling hardware devices but also
performing pure software operations
Searching through a large table of data for a special
string of characters
Code translation from ASCII to EBCDIC
Table sort routines
Mathematical routines

Assembly language: perform real-time operations

High-level languages: used to write those parts
that are not time critical
6

Converting Assembly Language Instructions

to Machine Code
An instruction can be coded with 1 to 6 bytes
Byte 1 contains three kinds of information
Opcode field (6 bits) specifies the operation (add, subtract,
move)
Register Direction Bit (D bit) Tells the register operand in REG
field in byte 2 is source or destination operand
1: destination
0: source
- Data Size Bit (W bit) Specifies whether the operation will be
performed on 8-bit or 16-bit data
0: 8 bits
1: 16 bits

 Byte 2 has three fields

Mode field (MOD)
Register field (REG) used to identify the register for the first operand
Register/memory field (R/M field)

Addressing Modes of 8086

The addressing mode describes the types of
operands and the way they are accessed for
executing an instruction. According to the flow of
instruction execution, the instructions may be
categorized as
1. Sequential control flow instructions and
2. Control transfer instructions.
9

Addressing Modes of 8086(Contd)

Sequential control flow instructions are the instructions
which after execution, transfer control to the next instruction
appearing immediately after it (in the sequence) in the
program. For example the arithmetic, logic, data transfer
and processor control instructions are Sequential control
flow instructions.

The control transfer instructions on the other

hand transfer control to some predefined address or the
address somehow specified in the instruction, after their
execution. For example INT, CALL, RET & JUMP
instructions fall under this category.
10

 The addressing modes for Sequential and control flow

instructions are explained as follows.
1. Immediate addressing mode:
In this type of addressing, immediate data is a part of
instruction, and appears in the form of successive byte or
bytes.
Example: MOV AX, 0005H.
In the above example, 0005H is the immediate data.
The immediate data may be 8-bit or 16-bit in size.
2. Direct addressing mode:
In the direct addressing mode, a 16-bit memory
address (offset) directly specified in the instruction as a part
of it.
Example: MOV AX, [5000H].
11

3. Register addressing mode:

In the register addressing mode, the data is stored in a
register and it is referred using the particular register. All the
registers, except IP, may be used in this mode.
Example: MOV BX, AX
4. Register indirect addressing mode:
Sometimes, the address of the memory location which
contains data or operands is determined in an indirect way,
using the offset registers. The mode of addressing is known
as register indirect mode.
In this addressing mode, the offset address of data is in
either BX or SI or DI Register. The default segment is either
DS or ES.
Example: MOV AX, [BX].
12

5. Indexed addressing mode:

In this addressing mode, offset of the operand is
stored one of the index registers. DS & ES are the default
segments for index registers SI & DI respectively.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in
SI in DS.
6. Register relative addressing mode:
In this addressing mode, the data is available at an
effective address formed by adding an 8-bit or 16-bit
displacement with the content of any one of the register BX,
BP, SI & DI in the default (either in DS & ES) segment.
Example: MOV AX, 50H [BX]
13

7. Based indexed addressing mode:

The effective address of data is formed in this
addressing mode, by adding content of a base register
(any one of BX or BP) to the content of an index register
(any one of SI or DI). The default segment register may be
ES or DS.
Example: MOV AX, [BX][SI]
8. Relative based indexed:
The effective address is formed by adding an 8 or
16-bit displacement with the sum of contents of any of the
base registers (BX or BP) and any one of the index
registers, in a default segment.
Example: MOV AX, 50H [BX] [SI]
14

Addressing Modes for control transfer instructions:

1. Intersegment

Intersegment direct

Intersegment indirect
2. Intrasegment

Intrasegment direct

Intrasegment indirect
1. Intersegment direct:
In this mode, the address to which the control is to be
transferred is in a different segment. This addressing mode
provides a means of branching from one code segment to
another code segment. Here, the CS and IP of the destination
address are specified directly in the instruction.
Example: JMP 5000H, 2000H;
Jump to effective address 2000H in segment 5000H.
15

2. Intersegment indirect:
In this mode, the address to which the control is to be
transferred lies in a different segment and it is passed to the
instruction indirectly, i.e. contents of a memory block containing
four bytes, i.e. IP(LSB), IP(MSB), CS(LSB) and CS(MSB)
sequentially. The starting address of the memory block may be
referred using any of the addressing modes, except immediate
mode.
Example: JMP [2000H].
Jump to an address in the other segment specified at
effective address 2000H in DS.
3. Intrasegment direct mode:
In this mode, the address to which the control is to be transferred
lies in the same segment in which the control transfers instruction lies and
appears directly in the instruction as an immediate displacement value. In
this addressing mode, the displacement is computed relative to the content
of the instruction pointer.
16
Example: JMP SHORT LABEL.

4. Intrasegment indirect mode:

In this mode, the displacement to which the
control is to be transferred is in the same segment in which
the control transfer instruction lies, but it is passed to the
instruction directly. Here, the branch address is found as
the content of a register or a memory location.
This addressing mode may be used in unconditional
branch instructions.
Example: JMP [BX]; Jump to effective address
stored in BX

17

Data Transfer Instructions - MOV

Mnemonic

Meaning

Format

Operation

Flags affected

MOV

Move

Mov D,S

(S) (D)

None

Destination

Source

Memory

Accumulator

Accumulator

Memory

Register

Register

Register

Memory

Memory

Register

Register

Immediate

Memory

Immediate

Seg reg

Reg 16

Seg reg

Mem 16

Reg 16

Seg reg

Memory

Seg reg

NO MOV
Memory
Immediate
Segment Register

EX:

Memory
Segment Register
Segment Register

MOV AL, BL

18

Data Transfer Instructions - XCHG

Mnemonic

Meaning

Format

XCHG

Exchange

XCHG D,S

Destination

Operation
(S)

(D)

Flags affected
None

Source

Accumulator Reg 16
Memory

Register

Register

Register

Register

Memory

Example: XCHG [1234h], BX

NO XCHG

MEMs
SEG REGs
19

Data Transfer Instructions LEA, LDS, LES

Mnemo
nic

Meaning

Format

LEA

Load
Effective
Address

LEA Reg16,EA

LDS

Load
Register
And DS

LDS Reg16,MEM32

Load
Register
and ES

LES Reg16,MEM32

LES

Operation
EA

(Reg16)

(MEM32) (Reg16)

Flags
affected
None

None

(Mem32+2) (DS)

(MEM32) (Reg16)

None

(Mem32+2) (DS)

LEA SI DATA (or) MOV SI Offset DATA

20

The XLAT Instruction

Mnemonic

Meaning

Format

XLAT

Translate

XLAT

Operation
((AL)+(BX)+(DS)0)

Flags
(AL)

None

Example:
Assume (DS) = 0300H, (BX)=0100H, and (AL)=0DH
XLAT replaces contents of AL by contents of memory location with
PA=(DS)0 +(BX) +(AL)
= 03000H + 0100H + 0DH = 0310DH
Thus
(0310DH) (AL)
21

Arithmetic Instructions: ADD, ADC, INC, AAA, DAA

Mnemonic

Meaning

Format

Operation

Flags
affected

ADD

Addition

ADD D,S

(S)+(D) (D)
carry
(CF)

ALL

ADC

Add with
carry

ADC D,S

INC

Increment by
one

INC D

AAA

ASCII adjust
for addition

AAA

If the sum is >9, AH

is incremented by 1

AF,CF

DAA

Decimal
adjust for
addition

DAA

Adjust AL for decimal

Packed BCD

ALL

(S)+(D)+(CF)
carry
(D)+1

(D)
(CF)

ALL

(D)

ALL but CY

22

Examples:
Ex.1

ADD AX,2
ADC AX,2

Ex.2 INC BX
INC WORD PTR [BX]
Ex.3 ASCII CODE 0-9 = 30-39h

MOV AX,38H
ADD AL,39H
AAA
ADD AX,3030H
Ex.4 AL contains 25 (packed BCD)
BL contains 56 (packed BCD)
ADD AL, BL
DAA

; (ASCII code for number 8)

; (ASCII code for number 9)
AL=71h
; used for addition
AH=01, AL=07
; answer to ASCII 0107
AX=3137

25
+ 56
-------7B 81
23

Arithmetic Instructions SUB, SBB, DEC, AAS, DAS, NEG

Mnemonic

Meaning

Format

Operation

SUB

Subtract

SUB D,S

SBB

Subtract
with
borrow

SBB D,S

DEC

Decrement
by one

DEC D

NEG

Negate

NEG D

DAS

Decimal
adjust for
subtraction

DAS

Convert the result in AL to

packed decimal format

All

AAS

ASCII
adjust for
subtraction

AAS

(AL) difference
(AH) dec by 1 if borrow

CY,AC

(D) - (S)
Borrow
(D) - (S) - (CF)

(D) - 1

Flags
affected

(D)
(CF)
(D)

(D)

All
All

All but CF
All

24

Examples: DAS
MOV BL, 28H
MOV AL, 83H
SUB AL,BL
DAS

; AL=5BH
; adjust as AL=55H

MOV AX, 38H

SUB AL,39H; AX=00FF
AAS
; AX=FF09 tens complement of -1
OR AL,30H ; AL=39

(Borrow one from AH )

25

Multiplication and Division

26

Multiplication and Division

Multiplication
(MUL or IMUL)

Multiplicand

Operand
(Multiplier)

Result

Byte*Byte

AL

Register or memory

AX

Word*Word

AX

Register or memory

DX :AX

Dword*Dword

EAX

Register or memory

EAX :EDX

Division
(DIV or IDIV)

Dividend

Operand
(Divisor)

Quotient: Remainder

Word/Byte

AX

Register or Memory

AL : AH

Dword/Word

DX:AX

Register or Memory

AX : DX

Qword/Dword

EDX: EAX

Register or Memory

EAX : EDX
27

Multiplication and Division Examples

Ex1:
Assume that each instruction starts from these values:
AL = 85H, BL = 35H, AH = 0H
1. MUL BL AL . BL = 85H * 35H = 1B89H AX = 1B89H
2. IMUL BL AL . BL = 2S AL * BL = 2S (85H) * 35H
= 7BH * 35H = 1977H 2s comp E689H AX.
AH
0085
H
3. DIV BL AX =
= 02 (85-02*35=1B)
1B
35 H
BL
AH AL
AX 0085 H
4. IDIV BL
=
=
1B 02
BL
35 H

AL

02

28

Ex2:

AL = F3H, BL = 91H, AH = 00H

1. MUL BL AL * BL = F3H * 91H = 89A3H AX = 89A3H
2. IMUL BL AL * BL = 2S AL * 2S BL = 2S (F3H) * 2S(91H) =
0DH * 6FH = 05A3H AX.

00 F 3H
00 F 3H
AX
3.IDIV BL
=
=
= 2 (00F3 2*6F=15H)
6
FH
2
'
S
(
91
H
)
BL
AH

AL

15
R

02
Q

POS
NEG 2s(02) = FEH

NEG

00 F 3H
AX
4. DIV BL
=
= 01(F3-1*91=62)
91
H
BL

AH
15

AL
FE

AH
62

AL
01

29

Ex3: AX= F000H, BX= 9015H, DX= 0000H

1. MUL BX = F000H * 9015H =

DX
8713

AX
B000

2. IMUL BX = 2S(F000H) * 2S(9015H) = 1000 * 6FEB =

DX

AX

06FE

B000

F 000 H
3. DIV BL =
= B6DH More than FFH Divide Error.
15 H

2' S ( F 000 H ) 1000 H

4. IDIV BL
=
= C3H > 7F Divide Error.
15 H
15 H

30

Ex4:

AX= 1250H, BL= 90H

AX 1250 H
1250 H
POS
POS
1250 H
1. IDIV BL
=
=
=
=
=
BL
NEG 2' sNEG 2' s(90 H )
70 H
90 H
= 29H (Q) (1250 29 * 70) = 60H (REM)
29H ( POS) 2S (29H) = D7H

R
60H

Q
D7H

1250 H
AX
2. DIV BL
=
= 20H1250-20*90 =50H
90
H
BL

R
50H
AH

Q
20H
AL

31

Logical Instructions
Mnemonic

Meaning

Format

Operation

Flags Affected

AND

Logical AND

AND D,S

(S) (D) (D)

OR

Logical Inclusive
OR

OR D,S

(S)+(D) (D)

XOR

Logical Exclusive
OR

XOR D,S

OF, SF, ZF, PF,

CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
None

NOT

LOGICAL NOT

Destination

Source

Register
Register
Memory
Register
Memory
Accumulator

Register
Memory
Register
Immediate
Immediate
Immediate

NOT D

(S) +

(D)(D)
_
(D) (D)

Destination

Register
Memory

32

LOGICAL Instructions
AND

Uses any addressing mode except memory-to-memory and

segment registers
Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
Examples:
AND BL, 0FH
AND AL, [345H]
OR
Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)
33

 XOR
Used in Inverting bits
xxxx xxxx XOR 0000 1111 = xxxxxxxx

-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit 5 of

register CL:
AND CL, OFCH ;
OR CL, 0C0H
;
XOR CL, 020H ;

1111 1100B
1100 0000B
0010 0000B

34

Shift and Rotate Instructions

SHR/SAL: shift logical left/shift
arithmetic left
SHR: shift logical right
SAR: shift arithmetic right
ROL: rotate left
ROR: rotate right
RCL: rotate left through carry
RCR: rotate right through carry

35

Logical vs Arithmetic Shifts

A logical shift fills the newly created bit position
with zero:
0
CF

An arithmetic shift fills the newly created bit

position with a copy of the numbers sign bit:

CF
36

Shift Instructions
Mnemo
-nic
SAL/SH
L

SHR

SAR

Meaning

Format

Shift
SAL/SHL D, Count
arithmetic
Left/shift
Logical left

Shift
logical
right

Shift
arithmetic
right

SHR D, Count

SAR D, Count

Operation

Flags
Affected

Shift the (D) left by the

number of bit positions
equal to count and fill the
vacated bits positions on
the right with zeros

CF,PF,SF,ZF
AF undefined
OF undefined
if count 1

Shift the (D) right by the

number of bit positions
equal to count and fill the
vacated bits positions on
the left with zeros

CF,PF,SF,ZF
AF undefined
OF undefined
if count 1

Shift the (D) right by the

number of bit positions
equal to count and fill the
vacated bits positions on
the left with the original
most significant bit

CF,PF,SF,ZF
AF undefined
OF undefined
if count 1
37

Allowed operands
Destination

Count

Register

Register

CL

Memory

Memory

CL

38

39

SHL Instruction
The SHL (shift left) instruction performs a logical
left shift on the destination operand, filling the
lowest bit with 0.
0
CF

Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL

40

Fast Multiplication
Shifting left 1 bit multiplies a number by 2
mov dl,5

Before:

00000101

=5

shl dl,1

After:

00001010

= 10

Shifting left n bits multiplies the operand by

2n
For example, 5 * 22 = 20
mov dl,5
shl dl,2

; DL = 20
41

Ex.
; Multiply

AX by 10

SHL AX, 1
MOV BX, AX
MOV CL,2
SHL AX,CL
ADD AX, BX

42

SHR Instruction
The SHR (shift right) instruction performs a logical
right shift on the destination operand. The highest
bit position is filled with a zero.
0
CF

Shifting right n bits divides the operand by 2n

MOV DL,80
SHR DL,1
SHR DL,2

; DL = 40
; DL = 10
43

SAR Instruction
SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.

CF

An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1
SAR DL,2

; DL = -40
; DL = -10
44

Rotate Instructions
Mnem
-onic

Meaning

Format

Operation

Flags Affected

ROL

Rotate
Left

ROL D,Count

ROR

Rotate
Right

ROR D,Count Rotate the (D) right by the

number of bit positions equal
to Count. Each bit shifted out
from the rightmost bit goes
back into the leftmost bit
position.

CF
OF undefined
if count 1

RCL

Rotate
Left
through
Carry

RCL D,Count

Same as ROL except carry is

attached to (D) for rotation.

CF
OF undefined
if count 1

RCR

Rotate
right
through
Carry

RCR D,Count Same as ROR except carry is

attached to (D) for rotation.

CF
OF undefined
if count 1 45

Rotate the (D) left by the

CF
number of bit positions equal
OF undefined
to Count. Each bit shifted out
if count 1
from the left most bit goes back
into the rightmost bit position.

ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the Carry
flag and into the lowest bit
No bits are lost

CF

MOV Al,11110000b
ROL Al,1

; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4

; DL = F3h
46

ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag and
into the highest bit
No bits are lost

CF

MOV AL,11110000b
ROR AL,1

; AL = 01111000b

MOV DL,3Fh
ROR DL,4

; DL = F3h
47

RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
CF

CLC
MOV BL,88H
RCL BL,1
RCL BL,1

;
;
;
;

CF = 0
CF,BL = 0 10001000b
CF,BL = 1 00010000b
CF,BL = 0 00100001b
48

RCR Instruction
RCR (rotate carry right) shifts each bit to the right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
CF

STC
MOV AH,10H
RCR AH,1

; CF = 1
; CF,AH = 00010000 1
; CF,AH = 10001000 0
49

Rotate Instructions
Destination

Count

Register

Register

CL

Memory

Memory

CL

50

Flag control instructions

MNEMONIC

MEANING

OPERATION

Flags
Affected

CLC

Clear Carry Flag (CF) 0

CF

STC

Set Carry Flag

(CF) 1

CF

CMC

Complement
Carry Flag

(CF) (CF)l

CF

CLD

Clear Direction
Flag

(DF) 0
SI & DI will be auto incremented while
string instructions are executed.

DF

Set Direction
Flag

(DF) 1
SI & DI will be auto decremented
while string instructions are executed.

DF

CLI

Clear Interrupt
Flag

(IF) 0

IF

STI

Set Interrupt
Flag

(IF) 1

IF

STD

51

Compare Instruction, CMP

Mnemo Meaning
nic

Format

Operation

CMP

CMP D,S

(D) (S) is used in CF, AF, OF,

Compare

Flags
Affected

setting or resetting the PF, SF, ZF

flags

Allowed Operands
(D) = (S)

; ZF=0

Destination

Source

Register

Register

(D) > (S)

; ZF=0, CF=0

Register

Memory

(D) < (S)

; ZF=0, CF=1

Memory

Register

Register

Immediate

Memory

Immediate

Accumulator

Immediate
52

String?
An array of bytes or words located in
memory
Supported String Operations
Copy (move, load)
Search (scan)
Store
Compare
53

String Instruction Basics

Source DS:SI, Destination ES:DI
You must ensure DS and ES are correct
You must ensure SI and DI are offsets into DS
and ES respectively
Direction Flag (0 = Up, 1 = Down)
CLD - Increment addresses (left to right)
STD - Decrement addresses (right to left)

54

String Instructions
Instruction prefixes

Prefix

REP

Used with

Meaning

MOVS
STOS

Repeat while not end of string

CX 0

REPE/REPZ

CMPS
SCAS

Repeat while not end of string

and strings are equal. CX 0
and ZF = 1

REPNE/REP
NZ

CMPS
SCAS

Repeat while not end of string

and strings are not equal. CX
55
0 and ZF = 0

Instructions
MnemoNic

meaning

format

Operation

Flags
effect
-ed

MOVS

Move string
DS:SI
ES:DI

MOVSB/ ((ES)0+(DI)) ((DS)0+(SI)) none

MOVSW (SI) (SI) 1 or 2
(DI) (DI) 1 or 2

CMPS

Compare
string
DS:SI
ES:DI

CMPSB/ Set flags as per

CMPSW ((DS)0+(SI)) - ((ES)0+(DI))
(SI) (SI) 1 or 2
(DI) (DI) 1 or 2

All
status
flags

56

MnemoNic

meaning

format

Operation

SCAS

Scan string
AX ES:DI

SCASB/
SCASW

LODS

Load string LODSB/

DS:SI AX LODSW

(AL or AX) ((DS)0+(SI))

(SI) (SI) 1 or 2

STOS

Store string STOSB/

ES:DI AX STOSW

((ES)0+(DI)) (AL or A) 1 or 2
(DI) (DI) 1 or 2

Set flags as per

(AL or AX) - ((ES)0+(DI))
(DI) (DI) 1 or 2

57

Branch group of instructions

Branch instructions provide lot of convenience to the
programmer to perform operations selectively, repetitively
etc.
Branch group of instructions

Conditional
jumps

Unconditional
jump

Iteration
instructions

CALL
instructions

Return
instructions

58

SUBROUTINE & SUBROUTINE HANDILING INSTRUCTIONS

Main program
Subroutine A
First Instruction
Call subroutine A
Next instruction

Return
Call subroutine A

Next instruction

59

 A subroutine is a special segment of program that can be called for

execution from any point in a program.
An assembly language subroutine is also referred to as a procedure.
Whenever we need the subroutine, a single instruction is inserted in to
the main body of the program to call subroutine.
To branch a subroutine the value in the IP or CS and IP must be
modified.
After execution, we want to return the control to the instruction that
immediately follows the one called the subroutine i.e., the original value
of IP or CS and IP must be preserved.
Execution of the instruction causes the contents of IP to be saved on
the stack. (this time (SP) (SP) -2 )
A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value
which is specified by the instructions operand is loaded into IP.
Examples: CALL 1234H
CALL BX
CALL [BX]
60

 Inter Segment
At starting CS and IP placed in a stack.
New values are loaded in to CS and IP given by the
operand.
After execution original CS, IP values placed as it is.
Far-proc
Memptr32
These two words (32 bits) are loaded directly into IP and
CS with execution at CALL instruction.

First 16 IP
Next 16 CS
61

Mnem- Meaning
onic
CALL

Format

Operation

Flags
Affected

Subroutine CALL operand Execution continues from none

call
the
address
of
the
subroutine specified by
the operand. Information
required to return back to
the main program such as
IP and CS are saved on
the stack.
Operand
Near-proc

Far proc
Memptr 16
Regptr 16
Memptr 32

62

RETURN
Every subroutine must end by executing an instruction that returns control
to the main program. This is the return (RET) instruction.
By execution the value of IP or IP and CS that were saved in the stack to
be returned back to their corresponding regs. (this time (SP) (SP)+2 )
Mnem Meaning
-onic

Format

RET

RET or
Return
RET operand program
(and CS
operands
added to
SP.

Return

Operation

Flags
Affected
to
the
main None
by restoring IP
for far-proc). If
is present, it is
the contents of

Operand
None
Disp16

63

Loop Instructions
These instructions are used to repeat a set of instructions several
times.
Format:
LOOP Short-Label
Operation: (CX) (CX)-1
Jump is initialized to location defined by short label if CX0.
otherwise, execute next sequential instruction.
Instruction LOOP works w.r.t contents of CX. CX must be
preloaded with a count that represents the number of times the
loop is to be repeat.
Whenever the loop is executed, contents at CX are first
decremented then checked to determine if they are equal to zero.
If CX=0, loop is complete and the instruction following loop is
executed.
If CX 0, content return to the instruction at the label specified in
the loop instruction.
64

LOOP Instruction contd.

General format : LOOP r8

; r8 is 8-bit signed value.

It is a 2 byte instruction.
Used for backward jump only.
Maximum distance for backward jump is only 128 bytes.
LOOP AGAIN is almost same as:

DEC CX
JNZ AGAIN

LOOP instruction does not affect any flags.

65

Mnemonic meaning

format

Operation

LOOP

Loop

Loop short-label

(CX) (CX) 1
Jump to location given by
short-label if CX 0

LOOPE/
LOOPZ

Loop while
equal/ loop
while zero

LOOPE/LOOPZ
short-label

(CX) (CX) 1
Jump to location given by
short-label if CX 0 and
ZF=1

LOOPNE/LOOPNZ
short-label

(CX) (CX) 1
Jump to location given by
short-label if CX 0 and
ZF=0

LOOPNE/ Loop while

LOOPNZ not equal/
loop while
not zero

66

Control flow and JUMP instructions

Unconditional Jump
Part 1

JMP AA

Unconditional JMP

Part 2
Skipped part
Part 3
AA

XXXX

Next instruction

JMP unconditional jump

JMP Operand
67

Unconditional Jump
Unconditional Jump Instruction
Near Jump or

Far Jump or

Intra segment Jump

Inter segment Jump
(Jump within the segment) (Jump to a different segment)
Is limited to the address with in
the current segment. It is achieved
by modifying value in IP

Permits jumps from one code

segment to another. It is
achieved by modifying CS and IP

Operands
Short label
Near label
Far label

Inter Segment Jump

Memptr16
Regptr16
memptr32

68

Inter Segment Jump

Conditional Jump
Part 1

Jcc AA

Conditional Jump

Part 2
NO
XXXX

condition

Skipped part

YES

Part 3
AA

XXXX

Next instruction

69

Conditional Jump instructions

Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte

opcode followed by 1-byte signed displacement (range of 128 to
+127).

Conditional Jump Instructions

Jumps based on
a single flag

Jumps based on
more than one flag

70

Conditional Jump Instructions

Mnemonic :

Jcc

Meaning :

Conditional Jump

Format :

Jcc operand

Operation :

If condition is true jump to the address specified by operand.

Otherwise the next instruction is executed.

Flags affected : None

71

TYPES
Mnemonic

meaning

condition

JA

Above

CF=0 and ZF=0

JB

Above or Equal

CF=0

JB

Below

CF=1

JBE

Below or Equal

CF=1 or ZF=1

JC

Carry

CF=1

JCXZ

CX register is Zero

(CF or ZF)=0

JE

Equal

ZF=1

JG

Greater

ZF=0 and SF=OF

JGE

Greater or Equal

SF=OF

JL

Less

(SF XOR OF) = 1

72

Mnemonic

meaning

condition

JLE

Less or Equal

((SF XOR OF) or ZF) = 1

JNA

Not Above

CF =1 or Zf=1

JNAE

Not Above nor Equal

CF = 1

JNB

Not Below

CF = 0

JNBE

Not Below nor Equal

CF = 0 and ZF = 0

JNC

Not Carry

CF = 0

JNE

Not Equal

ZF = 0

JNG

Not Greater

((SF XOR OF) or ZF)=1

JNGE

Not Greater nor Equal (SF XOR OF) = 1

JNL

Not Less

SF = OF
73

Mnemonic

meaning

condition

JNLE

Not Less nor Equal

ZF = 0 and SF = OF

JNO

Not Overflow

OF = 0

JNP

Not Parity

PF = 0

JNZ

Not Zero

ZF = 0

JNS

Not Sign

SF = 0

JO

Overflow

OF = 1

JP

Parity

PF = 1

JPE

Parity Even

PF = 1

JPO

Parity Odd

PF = 0

JS

Sign

SF = 1

JZ

Zero

ZF = 1

74

Jumps Based on a single flag

JZ

r8 ;Jump if zero flag set to 1 (Jump if result is zero)

JNZ

r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)

JS

r8 ;Jump if Sign flag set to 1 (result is negative)

JNS

r8 ;Jump if Not Sign (result is positive)

JC

r8 ;Jump if Carry flag set to 1

There is no jump
based on AC flag

JNC

r8 ;Jump if No Carry

JP

r8 ;Jump if Parity flag set to 1 (Parity is even)

JNP

r8 ;Jump if No Parity (Parity is odd)

JO

r8 ;Jump if Overflow flag set to 1 (result is wrong)

JNO

r8 ;Jump if No Overflow (result is correct)

75

JZ r8 ; JE (Jump if Equal) also means same.

JNZ r8 ; JNE (Jump if Not Equal) also means same.

JC r8 ;JB (Jump if below) and JNAE (Jump if Not Above

or Equal) also mean same.
JNC r8 ;JAE (Jump if Above or Equal) and JNB (Jump if
Not Above) also mean same.
JZ, JNZ, JC and JNC used after arithmetic operation
JE, JNE, JB, JNAE, JAE and JNB are used after a
compare operation.

JP r8 ; JPE (Jump if Parity Even) also means same.

JNP r8 ; JPO (Jump if Parity Odd) also means same.
76

Examples for JE or JZ instruction

Ex. for forward jump (Only examples for JE given)

CMP SI, DI

JE SAME
Should be
<=127
bytes

ADD CX, DX

;Executed if Z = 0

(if SI not equal to DI)

SAME: SUB BX, AX

;Executed if Z = 1
(if SI = DI)
77

Examples for JE or JZ instruction

Ex. for backward jump

BACK: SUB BX, AX

Should be
<= 128
bytes

; executed if Z = 1

(if SI = DI)

:
CMP SI, DI
JE BACK
ADD CX, DX

;executed if Z = 0
(if SI not equal to DI)

78

Jumping beyond -128 to +127?

What if
>127
bytes

Requirement

Then do this!

CMP SI, DI

CMP SI, DI

JE SAME

JNE NEXT

ADD CX, DX

JMP SAME

NEXT: ADD CX, DX

SAME: SUB BX, AX

SAME: SUB BX, AX

Range for JMP (unconditional jump) can be +215 = + 32K JMP instruction
discussed in detail later

79

Terms used in comparison

Above and Below used for comparing Unsigned nos.

Greater than and less than used with signed numbers.
All Intel microprocessors use this convention.
95H is above 65H
95H is less than 65H

Unsigned comparison - True

Signed comparison True
95H is negative, 65H is positive

65H is below 95H

Unsigned comparison - True

65H is greater than 95H

Signed comparison -

True
80

Jump on multiple flags

Conditional Jumps based on more than one flag are used after a CMP
(compare) instruction.

JBE or
JNA

Jump if Below or Equal

Jump if Not Above

Jump if

No Jump if

Ex.

Cy = 1 OR Z= 1

Cy = 0 AND Z = 0

CMP BX, CX

Below OR Equal

Surely Above

JBE BX_BE

BX_BE (BX is Below or Equal) is a symbolic location

81

Jump on multiple flags contd.

JNBE or
JA

Jump if Not (Below or Equal)

Jump if Above

Jump if

No Jump if

Ex.

Cy = 0 AND Z= 0

Cy = 1 OR Z = 1

CMP BX, CX

Surely Above

Below OR Equal

JA BXabove

BXabove (BX is above) is a symbolic location

82

Jump on multiple flags contd.

JLE or
JNG

Jump if Less than OR Equal

Jump if Not Greater than
Jump if

No Jump if

S = 1 AND V = 0
(surely negative)
OR (S = 0 AND V = 1)
(wrong answer positive!)
OR Z = 1 (equal)

S = 0 AND V = 0
(surely positive)
OR (S = 1 AND V = 1)
(wrong answer negative!)
AND Z = 0 (not equal)

i.e. S XOR V = 1 OR Z = 1

i.e. S XOR V = 0 AND Z = 0

83

Jump on multiple flags contd.

JNLE or
JG

Jump if Not (Less than OR Equal)

Jump if Greater than
Jump if

No Jump if

S = 0 AND V = 0
(surely positive)
OR (S = 1 AND V = 1)
(wrong answer negative!)
AND Z = 0 (not equal)

S = 1 AND V = 0
(surely negative)
OR (S = 0 AND V = 1)
(wrong answer positive!)
OR Z = 1 (equal)

i.e. S XOR V = 0 AND Z = 0

i.e. S XOR V = 1 OR Z = 1

84

Jump on multiple flags contd.

JL or
JNGE

Jump if Less than

Jump if Not (Greater than OR Equal)
Jump if

No Jump if

S = 1 AND V = 0
(surely negative)
OR (S = 0 AND V = 1)
(wrong answer positive!)

S = 0 AND V = 0
(surely positive)
OR (S = 1 AND V = 1)
(wrong answer negative!)

i.e. S XOR V = 1

i.e. S XOR V = 0

When S = 1, result cannot be 0

When S = 0, result can be 0

85

Jump on multiple flags contd.

JNL or
JGE

Jump if Not Less than

Jump if Greater than OR Equal
Jump if

No Jump if

S = 0 AND V = 0
(surely positive)
OR (S = 1 AND V = 1)
(wrong answer negative!)

S = 1 AND V = 0
(surely negative)
OR (S = 0 AND V = 1)
(wrong answer positive!)

i.e. S XOR V = 0

i.e. S XOR V = 1

When S = 0, result can be 0

When S = 1, result cannot be 0

86

Near Jump
Near Jump
Direct Jump
(common)

Indirect Jump
(uncommon)

Short Jump

Long Jump

2 bytes

3 bytes

EB r8

E9 r16

range + 27

range +215

2 or more bytes
Starting with FFH
Range: complete
segment

3 Near Jump and 2 Far Jump instructions have the same mnemonic
JMP but different opcodes
87

Short Jump
2 byte (EB r8) instruction Range: -128 to +127 bytes
Backward jump: Assembler knows the quantum of jump.
Generates Short Jump code if <=128 bytes is the required jump
Generates code for Long Jump if >128 bytes is the required jump

Forward jump: Assembler doesnt know jump quantum in pass 1.

Assembler reserves 3 bytes for the forward jump instruction.
If jump distance turns out to be >128 bytes, the instruction is
coded as E9 r16 (E9H = Long jump code).
If jump distance becomes <=128 bytes, the instruction is coded as
EB r8 followed by code for NOP (E8H = Short jump code).
88

Short Jump contd.

SHORT Assembler Directive

Assembler generates only 2 byte Short Jump code for forward jump, if the
SHORT assembler directive is used.
JMP SHORT
Programmer should ensure that the
Jump distance is <=127 bytes

SAME

:
:
SAME:

MOV CX, DX

89

Long Jump
3-byte (E9 r16) instruction Range: -32768 to +32767 bytes

Long Jump can cover entire 64K bytes of Code segment

CS:0000H
Long Jump can
handle it as jump
quantum is <=32767

CS:8000H

JMP FRWD
:
:

FRWD = CS:FFFFH

90

Long Jump contd.

It can cover entire 64K bytes of Code segment

Long Jump can

handle it as jump
quantum is
<=32768

BKWD = CS:0000H
CS:8000H

JMP BKWD
:
:

CS:FFFFH

91

Long Jump or Short Jump?

CS:0000H

:
:

Can be treated
as a small
(20H) backward
branch!

CS:000DH

JMP FRWD

CS:0010H

Jump distance
=FFE0H. Too
very long
forward jump

:
FRWD= CS:FFF0H
CS:FFFFH

92

Long Jump or Short Jump?

CS:0000H

:
:

Can be treated
as a small
(20H) forward
branch!

BKWD= CS:0010H

:
:

Jump distance
=FFE0H. Too
very long
backward jump

JMP BKWD
CS:FFF0H
CS:FFFFH

93

Intra segment indirect Jump

Near Indirect Jump is uncommon.
Instruction length: 2 or more bytes
Range: complete segment
Ex.1: JMP DX
If DX = 1234H, branches to CS:1234H
1234H is not signed relative displacement
Ex. 2: JMP wordptr 2000H[BX]
BX 1234H

DS:3234H 5678H

Branches to

DS:3236H AB22H

CS:5678H
94

Far Jump
Far Jump

Direct Jump
(common)

Indirect Jump
(uncommon)

5 bytes
EA,2 byte offset, 2 byte segment
Range: anywhere

2 or more bytes
Starting with FFH
Range: anywhere

3 Near Jump and 2 Far Jump instructions have the same mnemonic
JMP but different opcodes
95

Inter segment Direct Jump

Also called Far Direct Jump
It is the common inter segment jump scheme
It is a 5 byte instruction
1 byte opcode (EAH)
2 byte offset value
2 byte segment value

Ex. JMP Far ptr LOC

96

Inter segment Indirect Jump

Instruction length depends on the way jump location is

specified
It can be a minimum of 2 bytes

Ex. JMP DWORD PTR 2000H[BX]

97

Inter segment Indirect Jump

Also called Far Indirect Jump

It is not commonly used
Instruction length is a minimum of 2 bytes.
It depends on the way jump location is specified
Ex. JMP DWORD PTR 2000H[BX]
BX

1234H

Branches to
ABCDH:5678H

DS:3234H

5678H

DS:3236H

ABCDH

It is a 4-byte instruction

98

Machine control instructions

HLT instruction HALT processing
the HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only way to get the processor
out of the halt state are with an interrupt signal on the INTR pin or an interrupt
signal on NMI pin or a reset signal on the RESET input.
NOP instruction
this instruction simply takes up three clock cycles and does no
processing. After this, it will execute the next instruction. This instruction is
normally used to provide delays in between instructions.
ESC instruction
whenever this instruction executes, the microprocessor does NOP or
access a data from memory for coprocessor. This instruction passes the
information to 8087 math processor. Six bits of ESC instruction provide the
opcode to coprocessor.
when 8086 fetches instruction bytes, co-processor also picks up these
bytes and puts in its queue. The co-processor will treat normal 8086
instructions as NOP. Floating point instructions are executed by 8087 and
during this 8086 will be in WAIT.
99

Machine control instructions contd

LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during
execution of the instruction, control of system bus is not taken by other
microprocessor.
in multiprocessor systems, individual microprocessors are connected
together by a system bus. This is to share the common resources. Each
processor will take control of this bus only when it needs to use common
resource.
the lock prefix will ensure that in the middle of an instruction, system
bus is not taken by other processors. This is achieved by hardware signal
LOCK available on one of the CPU pin. This signal will be made active
during this instruction and it is used by the bus control logic to prevent
others from taking the bus.
once this instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU will not do
any processing during this. It will continue to be in idle state until TEST pin
of 8086 becomes low or an interrupt signal is received on INTR or NMI. On
valid interrupt, ISR is executed and processor enters the idle state again.
100

Thank You

101