Chapter 5

Elements of Physical Design

Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Jhongli, Taiwan

Outline
Basic Concepts
Layout of Basic Structures
Cell Concepts
MOS Sizing
Physical Design of Logic Gates
Design Hierarchies

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Basic Concepts

Physical design

The actual process of creating circuits on silicon

During this phase, schematic diagrams are carefully
translated into sets of geometric patterns that are
used to define the on-chip physical structures

Every layer in the CMOS fabrication sequence is

defined by a distinct pattern
The process of physical design is performed using
a computer tool called a layout editor
A graphics program that allows the designer to specify
the shape, dimensions, and placement

Complexity issues are attacked by first designing

simple gates and storing their descriptive files in
a library subdirectory or folder
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Basic Concepts
The gates constitute cells in the library

Library cells are used as building blocks by

creating copies of the basic cells to
construct a larger more complex circuit
This process is called instantiate of the cell
A copy of a cell is called an instance

Much of the designers work is directed

toward the goal of obtaining a fast circuit in
the minimum amount of area
Small changes in the shapes or area of a polygon
will affect the resulting electrical characteristics
of the circuit
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

CAD Toolsets
Physical design is based on the use of CAD
tools
Simplify the procedure and aid in the verification
process

Physical design toolsets

Layout editor
Extraction routine
Layout versus schematic (LVS)
Design rule checker (DRC)
Place and route routine
Electrical rule checker (ERC)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Layout of Basic Structures

The masking sequence of the P-substrate

technology was established as

Start with P-type substrate

nWell
Active
Poly
pSelect
nSelect
Active Contact
Poly contact
Metal1
Via
Metal2

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Layout of Basic Structures

It is worth remembering that the features on
every level have design rule specifications for
the minimum width w of a line, and a minimum
edge-to-edge spacing s between adjacent
polygons
For example,
w

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Rules
Design rules (layout rules)
Provide a necessary communication link between
circuit designers and process engineers during
manufacturing phase
The goal of design rules is to achieve the optimum
yield of a circuit with the smallest area cost

Design rules specify to the designer certain

geometric constraints on the layout artwork
so that the patterns on the processed wafer
will preserve the topology and geometry of
the designs
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Rules
The design rules primarily address two issues
The geometrical reproduction of features that can
be reproduced by the mask-making and
lithographical process
The interactions between different layers

Lambda-based rules
Based on a single parameter, lambda, which
characterizes the linear feature the resolution
of the complete wafer implementation process

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Examples of Design Rules

Different Potential

Same Potential

0
or
6

Well
10

Active

Polysilicon
3

2
3

Metal1

Contact
or Via
Hole

2
3

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Jin-Fu Li, EE, NCU

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Transistor

Transistor Layout

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Jin-Fu Li, EE, NCU

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Design Rules for Vias & Contacts

2
4

Via
1

1
5

Metal to
1
Active Contact

Metal to
Poly Contact
3

2
2

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Jin-Fu Li, EE, NCU

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Design Rule Checker

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Jin-Fu Li, EE, NCU

13

Layouts of PMOS & NMOS

NMOS
L

Poly
n+

n+

n+

Poly

n+

PMOS
L

Poly

p+

p+

p+

Poly

p+

N-well
P
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N-well
Jin-Fu Li, EE, NCU

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The Layout of a CMOS Inverter

A transistor-level CMOS inverter & the
corresponding layout
Vdd
Vdd

Vout

Vin

Vout

Vin

Vss

Vss
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Layouts of a 2-Input NAND Gate

Vdd

Vdd

z
z

a
b

a
b
Vss

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Vss

16

Layouts of a 2-Input NOR Gate

Vdd

a
b

Vdd

Vss

Vss
b

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Cell Concepts
The basic building blocks in physical design
are called cells
Logic gates as basic cells
XNOT
Vdd

XNAND2
Vdd

in

out

Vss

Vss

Vdd

XNOR2
Vdd

in1

out

in2
Vss

Vss

Vdd
in1
in2
Vss

Vdd
out
Vss

Note that power supply ports for Vdd and Vss are
chosen to be at the same locations for every cell
The width of each cell depends on the transistor
sizes and wiring used at the physical level
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Cell Creation Using Primitive Cells

Create a new cell providing the function
f=ab
Vdd
a

b
Vss

2XNOT+XNAND2
Vdd
f

a
b
Vss
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Layout of Cells
Vdd & Vss power supply lines
Vdd
PMOSs

nWell
Dm1-m1
P-substrate

Pm1-m1

NMOSs

Vss

Dm1-m1: edge-to-edge distance between Vdd and Vss

Pm1-m1: distance between the middle of the Vdd and
Vss lines
Pm1-m1=Dm1-m1+Wdd, where Wdd is the width of the
power supply lines
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Layout of Cells
Layout styles of transistors
Vdd
WP
WP

Wn
Wn
Vss

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Effect of Layout Shapes

Larger spacing between Vdd and Vss
Vdd

Vss

Smaller spacing between Vdd and Vss

Vdd
A

Vss
Advanced Reliable Systems (ARES) Lab.

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Routing Channels
Interconnection routing considerations are very
important considerations for the Vss-Vdd spacing

In complex digital systems, the wiring is often more

complicated than designing the transistor arrays
The general idea for routing
Metal3
Wiring

Vdd
Vss

cell1

cell2

cell3

cell4

cell5

Routing
Channel

Metal1
Wiring

Vdd
Vss

cell7

cell6

cell8

cell9

Routing
Channel

Metal2
Wiring
Metal1
Wiring

Vdd
Vss

cell10

cell11

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cell12

Jin-Fu Li, EE, NCU

cell13

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High-Density Techniques
Alternate Vdd and Vss power lines and share
them with cells above and below
For example,
Vdd
Vss
Vdd
Vss
Vdd

Logic cells
Inverted logic cells
Logic cells
Inverted logic cells

Since no space is automatically reserved for routing,

this scheme allows for high-density of placement of
cells
The main drawback is that the connection between
rows must be accomplished by using Metal2 or higher
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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High-Density Techniques
MOS transistor placement
PMOS transistors
Vdd
nWell

PMOS transistors

P-substrate

NMOS transistors

P-substrate

NMOS transistors

Vss

nWell
PMOS transistors
Vdd
PMOS transistors

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Port Placement
An example of the port placement in a cell
Vdd

Metal1
input

Metal1
output

Vss

To routing channel

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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MOS Sizing in Physical Design

A minimum-size MOS transistor is the
smallest transistor that can be created using
the design rule set
L
Scaling of the unit transistor
L

L
W

2X

4W

2W

4X

L
W

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2X

Jin-Fu Li, EE, NCU

2W

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Physical Designs of Complex Gates

Vdd

D
B
A

z
Z

B
Vss

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

28

Physical Design of XNOR Gate (1)

A
B

Z
Z

Vdd

B
A
Vss

B
Z

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Physical Design of XNOR Gate (2)

A
B
Z

Vdd

Vss
z

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

30

Automation of Physical Design

A

E
Vdd

E
D

C
E

B
Vss

Vdd
P

Vss
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Standard-Cell Physical Design

WVdd

Wp

Dnp

Wn
a

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

WVss
32

Standard-Cell Physical Design

Vdd

Vdd

Vss
a

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Vss
a

Jin-Fu Li, EE, NCU

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Gate-Array Physical Design

Vdd

Vss

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Gate-Array Physical Design

Vdd
Gate array cells

Routing channels
Vss

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

35

Sea-of-Gate Physical Design

well contacts
Vdd supply

P-transistors

poly gates

N-transistors

Vss supply
substrate contacts
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

36

Sea-of-Gate Physical Design

a

a
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

37

CMOS Layout Guidelines

Run VDD and VSS in metal at the top and bottom
of the cell
Run a vertical poly line for each gate input
Order the poly gate signals to allow the
maximal connection between transistors via
abutting source-drain connection
Place n-gate segments close to VSS and p-gate
segments close to VDD
Connection to complete the logic gate should be
made in poly, metal, or, where appropriate, in
diffusion
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

38

Guidelines for Improving Density

Better use of routing layers routes can
occurs over cells
More merged source-drain connections
More usage of white space in sparse gates
Use of optimum device sizes the use of
smaller devices leads to smaller layouts

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

39

Layout Optimization
Vary the size of the transistor according to the
position in the structure
Vdd
clk
F
A<0>
F

A<1>
A<2>
A<3>

Vss
clk A<3> A<2> A<1> A<0>

In submicron technologies, where the source/drain

capacitances are less, such that this improvement is
limited
Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Layout Optimization
2
A
A
B
C
D

D
1

Vdd

Right

Wrong

Vss
A

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A
Jin-Fu Li, EE, NCU

D
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Layouts of Transmission Gates

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42

Routing to Transmission Gates

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43

2-Input Multiplexer

c
a
z

-c

b
c

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-c

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44

Design Hierarchies
Layout level

cell1

cell2

celln

Cell library

Subsystems
Module 1

Module m

Module 4

Module 1
Module 3
Module 2

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Module 5

Chips

Module 6
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45

Summary
Basic physical design concepts have been
introduced
Cell concepts have also presented
Layout optimization guidelines have been
summarized
Design hierarchy has been briefly introduced

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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