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Final Project Report Digital Clock | PDF | Computer Engineering | Electronics
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Final Project Report Digital Clock

Our group chose to build a digital clock to understand its functions. The clock uses JK flip-flops and counters to track time in hours, minutes and seconds. It resets at midnight. The circuit was designed but did not work properly, possibly due to issues like dirty jumper wires, soldering problems, or a damaged timer chip. The second section counter did not function, preventing the whole clock from working since it uses asynchronous counters.
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100% found this document useful (1 vote)
4K views7 pages

Final Project Report Digital Clock

Our group chose to build a digital clock to understand its functions. The clock uses JK flip-flops and counters to track time in hours, minutes and seconds. It resets at midnight. The circuit was designed but did not work properly, possibly due to issues like dirty jumper wires, soldering problems, or a damaged timer chip. The second section counter did not function, preventing the whole clock from working since it uses asynchronous counters.
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction

Our group has choose to build a digital clock because many people use
digital clock in their daily lives so we want to build a digital clock so that we
can know how to build and understands more the function of digital clock.
We know that time in system, 60 second equal to 1 minute and 60 minute
equal to 1 hour. Hence the minute section is derived by second section and
one hour section derived by minute section. Each of the minute and second
section has been designed to give a count from 00 to 59 after which it resets
to 00 and the hour section to give a count from 00 to 24 hours after which it
resets to 00. For each cycle of 00 to 59 in second sections the minute section
increase its count by 1. Similarly for each cycle of 00 to 59 in minute section
the hour section increases its count by 1. In this way when the clock reaches
23hrs 59mins 59secs. Each of the section reset to 00 giving us a display
00.00.00 popularly known as the 0thhour. Now, without wasting any time we
straight away move into the discussion with our project with emphasis on
different sections considering the modules.

Related Work
In our design, JK-flip-flop with reset function is the most important basic
block used to create counters. We briefly introduce the implementation of JKflip-flop and JK-flip-flop with reset function in the next section. The JK-flip-flop
augments the behavior of the SR flip flop (J=SET, K=RESET) by interpreting
the S=R=1 condition as flip or toggle command. Specifically, the
combination of j=1, K=0 is a command to set the flip-flop; the combination
J=K=1 is a value. The flip flop is negative edge triggered (falling clock
pulse).

Components Used
Table 1 show the component that has been used in our project:
Component
IC 7408

Quantity
5

IC 7400
IC 7447
IC 74107
IC 555
7-Segment display
Resistances 180 Ohm
Resistances 10 K Ohm
Resistances 22 K Ohm
Capacitor 10uf
Capacitor 100 uf

3
6
11
1
6
42
1
1
1
1

Methodology
To develop DIGITAL CLOCK using 7 segment display. It shows hours, minute
and second. Make it by using discrete components:
a. Using IC 7408, 7400, 7447 & 74107.
b. Designed Block Diagram, Logic Diagram and Circuit Diagram
c. Component Description and Working

Result and Discussion


Our project has divided into four modules. They are as follows:
A. 155 IC Timer Section
The 555 timer IC is an integrated chip (IC) used in a variety of timer,
pulse generator and oscillator application. The 555 timer which give one Hz
frequency to JK FLIP FLOP
B. Second section
We used total four JK FLIP FLOP (74107) and one single IC contains two flip
flops. We use three flip flop which give 0 to 7 outputs and remaining other 4
flip flop give 0 to 15. But we know digital clock always displays 5 & 9 in
second. Instead of it we required 0 to 5 outputs in single seven segment
display so we connect the NAND gate which gives low logic to flip flop and
not allow it to exceeding from 5 digit number which is our requirement on
single seven segment display. On the other hand, the remaining four flip flop
which give 0 to 15 but our requirement that it should only display 0 to 9

count not to exceeding from it so we also here need NAND gate to stop it
and give us our prerequisite which is 0 to 9 counting on single seven
segment display. When the circuit will display successfully 5 & 9 in each
seven segment display with the help of driver IC 7447 then it gives pulse to
minute section.
C. Minute section
Repeating the same circuit operation which we had previously used for
the second section but this portion activates when section more than from 5
& 9 second displays. We used total four JK FLIP FLOP IC (74107) and one
single IC contains two flip flops. We use three flip flop which give 0 to 7 count
output and remaining after other 4 flip flop give 0 to 15. But we know digital
clock always displays 5 & 9 in minute but instead of it we required 0 to 5
count output in single seven segment displays so we connect the NAND gate
which give low logic to flip flop and not allow it to exceeding from 5 digit
number which is our requirement on single seven segment display. On the
other hand the remaining four flip flop which want to give 0 to 15 but our
requirement that it should display 0 to 9 count not to exceeding from it so we
also here need NAND gate to stop it give us our prerequisite which is 0 to 9
count. When the circuits will displays successfully 5 & 9 in each seven
segments display with the help of driver IC 7447 then it gives pulse to hour
section.
D. Hour section
Designing the circuit in such a way so that the output resets to 0 0 0
automatically displaying 11.59.59. The counting proceeds with a frequency
of one pulse peer hour coming from minute section. We used three J-K flip
flop IC (74107) and in a single J-K flip flop IC it contain two flip flop. We know
that hour would show 2 & 4 in each seven segment displays not greater than
that number. So we need 0 to 2 displays count on first segment and 0 to 4
counts on other segment. In hour section same as previous section we used
J-K flip flop to connect all needed component we need 0 to 2 display on single
seven segment due to prevent it from exceeding we similarly as usual used
NAND gate to clear the two flip flop which they want to show 0 to 4 count but
our requirement is to only want to display 0 to 2. On the other hand
remaining flip flop contain which is four out of six which would like to show 0
to 15 but our required to display only 0 to 9 count on single seven segment
display so we connect the same as previous we had done used NAND gate to
clear when it want to increase but our target display only 0 to 2 and 0 to 4 on
each seven segment only not above than that.

Conclusion

The circuit was purely designed with the basic knowledge on sequential
circuit designing and with the components provided by the authority. The
clock is expected to operate normally with desired accuracy. Unfortunately
our clock did not operate like it supposed to. The circuit from the second
section does not functioning well. Automatically, the minute and hour circuits
cannot be function since our clock use asynchronous counter which mean,
the minute input is from second section while the hour input is from minute
section. Once one circuit not functioning, the rest circuit will be not
functioning too. Therefore, we have made some analysis of why our clock
did not functioning:

Jumper wires are dirty and have kinked end it is because the metal
wire inside the jumper wire is multiple wire which is difficult to use.
Lines of tinned/copper of the strip board running up and down the
board.
Leakage current which lead to more heating issues and can easily
affect other components.
Incorrectly wired to IC
The timer does not work because the 555 timer maybe damaged.
Soldering problems
- The surface of the joint did not melt completely.
- The surfaced of the joint may appear frosted, crystalline or
rough.
- The solder has not yet flowed well which cause the residue of
burnt flux will make fixing this joint difficult.
- The solder has wetted the lead nicely but it has not formed a
good bond with the pad.
- The solder not wetted the pin at all and has only partially
wetted the pad.
- It is entirely possible that this blob of solder wets neither the
pin nor the pad and it is not a reliable electrical connection.
- The left two solder joints have melted together, forming an
unintended connection between the two.

Figure 1 Logic Diagram

Figure 2 Block Diagram

Figure 3 The simulation of our circuit

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