College of Engineering

Department of Electromechanical Engineering

Digital Logic Design

Group Project

Section B

Hailegebriel Kibebew ETS0717/14

Hawi Guteta ETS0746/14

Haylemaryam Daget ETS0755/14

Husni Jilalu ETS0819/14

Submitted to: Inst. Mitiku Berhe

Submission Date:
Contents
Components Used..................................................................................................................................8
Circuit Description..............................................................................................................................10
555 Timer as Clock Generator........................................................................................................10
CD4026 ICs for Digit Counting......................................................................................................10
Reset and Overflow Management using AND Gates (IC 7411)....................................................10
7-Segment Displays..........................................................................................................................11
Power Supply...................................................................................................................................11
Working Principle...............................................................................................................................12
Gate and IC Operation...........................................................................................................................14
7.1. 555 Timer IC................................................................................................................................14
7.2. CD4026 IC (Decade Counter and Display Driver)........................................................................14
7.3. IC 7411 – Triple 3-Input AND Gate..............................................................................................15
Integration of All Components..........................................................................................................16
Conclusion............................................................................................................................................19
 Introduction
In today’s digital age, electronic counters have become fundamental components in a wide range
of devices, including digital watches, scoreboards, odometers, production line monitors, and
frequency counters. Counters are essentially sequential circuits designed to count pulses and
represent the count either in binary or in decimal form. One of the most practical and educational
applications of such counters is the implementation of a digital clock.

A digital clock typically consists of counters that count seconds, minutes, and hours, and display
the time in a human-readable numeric format. Instead of using microcontrollers or advanced
embedded systems, this project focuses on building a 6-digit digital clock using basic and
widely available integrated circuits (ICs), specifically the CD4026 decade counter, 555 timer,
and 7411 AND gates. The use of such components not only simplifies the circuit design but also
offers a valuable learning opportunity to understand the fundamentals of digital electronics.

The CD4026 is a decade counter with an integrated 7-segment decoder, meaning it can count
from 0 to 9 and directly drive a 7-segment display without the need for an additional BCD to 7-
segment converter. The 555 timer, configured in astable mode, acts as the clock pulse generator
— it provides the timing signal that keeps the counter incrementing at a steady rate. AND gates
(specifically from the IC 7411) are used to detect specific conditions such as the end of a digit
cycle (e.g., when seconds reach 60), and to control the carry-over to the next digit.

In this project, six CD4026 ICs are connected in a cascading manner, each driving one digit of a
7-segment display. These digits represent seconds (2 digits), minutes (2 digits), and hours (2
digits), thus forming a complete HH:MM:SS format. The logic design ensures that the count
progresses correctly, resets at appropriate boundaries (59 seconds, 59 minutes, and 23 hours),
and visually represents the current time through the displays.

This implementation demonstrates the practical use of combinational and sequential logic,
particularly the use of flip-flops, counters, logic gates, and display drivers. It provides hands-on
experience with circuit design, logic timing, signal propagation, and modular hardware
architecture.

Overall, the digital clock project not only simulates a real-time counting system but also helps
students strengthen their understanding of core digital logic concepts. It’s a foundational step
toward designing more complex digital systems and embedded applications.
 Objective
The primary objective of this project is to design, construct, and simulate a fully functional 6-
digit digital clock using basic digital logic components. The system aims to display time in the
format of HH:MM:SS (Hours:Minutes:Seconds) and count accurately from 00:00:00 to
23:59:59, resetting and incrementing each unit at the appropriate boundary.

To achieve this, the project employs:

 A 555 timer IC, configured in astable mode, to serve as a continuous clock pulse
generator at a frequency of approximately 1 Hz (one pulse per second).
 CD4026 ICs, which act as decade counters that can count from 0 to 9 and directly drive
7-segment displays. These are cascaded to represent each digit of the clock.
 IC 7411 (Triple 3-input AND gates), used to identify when a particular stage of the
counter (e.g., seconds, minutes, or hours) has reached its limit and must reset, while also
sending a carry signal to the next digit.

Through this design, the clock will perform the following actions:

 Increment seconds every second, using the output of the 555 timer.
 Reset the seconds to 00 after reaching 59, and increment the minute digits accordingly.
 Reset the minutes to 00 after reaching 59, and increment the hour digits.
 Reset the hours to 00 after reaching 23, completing a 24-hour cycle.

Beyond its technical functionality, this project also aims to:

 Reinforce the understanding of digital counters, logic gates, and timing circuits.
 Provide hands-on experience with ICs, cascading logic, and display drivers.
 Simulate a real-time system using sequential logic rather than programmable
microcontrollers, thus deepening knowledge of circuit-level digital logic.
 Demonstrate how multiple logic blocks can be integrated to form a complete and
synchronized digital system.

In essence, the project serves both a practical purpose (building a working digital timekeeping
system) and an educational purpose (enhancing foundational knowledge in Digital Logic
Design).
Methodology
The methodology of this project involves a structured process that combines theoretical
knowledge of digital logic circuits with practical simulation and implementation. The following
steps were undertaken to develop the 6-digit digital clock:

1. Requirement Analysis
The first step was to understand the functional requirements of a digital clock. This
includes counting seconds, minutes, and hours up to 23:59:59 and displaying them in real
time using seven-segment displays.
2. Component Selection
Based on the requirements, suitable ICs were selected:
o 555 Timer to generate a 1 Hz clock pulse.
o CD4026 ICs for counting and driving 7-segment displays.
o IC 7411 (Triple 3-input AND gate) to detect overflow conditions in seconds,
minutes, and hours and control cascading.
3. Circuit Design
A schematic was developed where the 555 Timer was configured in astable mode to
produce a steady clock signal. Six CD4026 ICs were arranged in a cascaded structure to
represent each digit of the clock. Logical connections were made to carry out signals
between counters, and AND gates were inserted to manage valid time transitions.
4. Simulation and Testing
The circuit was simulated using [insert your software tool: e.g., Proteus, Logisim,
Multisim]. Each stage of counting (seconds, minutes, and hours) was tested to ensure
correct incrementing, carry propagation, and reset behavior.
5. Validation and Debugging
Special attention was given to the behavior at boundary values (e.g., 59 seconds rolling
over to 00 and incrementing minutes). Adjustments were made to the placement of AND
gates and reset signals to maintain time accuracy.
6. Documentation
The final design and working principle were documented, including component
functions, gate-level logic, and observations from the simulation.
Block Diagram
At the heart of the system is a 555 Timer IC configured in astable mode. It continuously
generates clock pulses at a frequency of approximately 1 Hz (1 pulse per second). This clock
signal is fed into the first CD4026 counter, which begins counting from 0 to 9. Each CD4026
drives a 7-segment display to show the digit.

When a CD4026 reaches the count of 9 and resets to 0, it produces a carry-out signal. This
carry-out is used either directly or through an AND gate (IC 7411) to increment the next counter
in the chain.

The system consists of six CD4026 ICs, each responsible for one digit of the final 6-digit
display:

 The first two counters represent seconds (00–59),

 The next two counters represent minutes (00–59),
 The last two counters represent hours (00–23).

To ensure valid time counting, logic gates (AND gates from IC 7411) are placed between some
stages. These detect when a digit reaches a preset maximum (like 6 in minutes/seconds or 3 in
the tens of hours place) and reset the appropriate counters to maintain valid time formatting.
Components Used
The 6-digit digital clock project uses fundamental digital and analog components that are widely
available and easy to interface. Each component serves a specific purpose, whether it's for pulse
generation, counting, logic control, or display. Below is a detailed list of the components used
and their descriptions:

1. 555 Timer IC

 Type: Analog timer IC

 Function: Generates a continuous stream of square wave pulses when configured in
astable mode.
 Role in Circuit: Acts as the clock pulse generator, providing 1 Hz pulses (one pulse per
second) to drive the counters.
 Pins of interest:
o Pin 3: Output (connects to first CD4026 input)
o Pins 6 & 2: Threshold and Trigger (connected together)
o Pin 1 & 8: Ground and VCC

2. CD4026 IC (×6)

 Type: Decade counter with 7-segment display driver (CMOS 4000 series)
 Function: Counts from 0 to 9 and sends output directly to a 7-segment display.
 Role in Circuit: Each CD4026 controls one digit of the 6-digit clock. The IC also
handles display encoding internally, eliminating the need for a separate BCD-to-7-
segment decoder.
 Key Pin Functions:
o Pin 1 (CLK): Clock input (positive edge triggered)
o Pin 5 (CO): Carry-out (used to increment the next digit)
o Pin 15 (RST): Reset pin (resets count to 0 when HIGH)
o Pins 10–7, 6, 11, 9: Segment outputs for driving 7-segment display
o Pin 3 (DE): Display enable (usually grounded)

3. IC 7411 – Triple 3-Input AND Gate (×1)

 Type: Logic gate IC from TTL family (7400 series)

 Function: Performs logical AND operation on three input signals.
 Role in Circuit: Detects specific conditions (like when a counter reaches “6” or “3”) by
checking the outputs of the CD4026. When a specific time condition is met (e.g., seconds
= 60), the AND gate outputs HIGH to trigger a reset or increment the next stage.

4. 7-Segment Display (Common Cathode) (×6)

 Type: LED-based numeric display

  Function: Displays digits 0–9 using 7 individual segments labeled A to G.
 Role in Circuit: Visually shows each digit of the time — two digits for hours, minutes,
and seconds respectively. Each display is driven directly by a corresponding CD4026 IC.

5. Resistors

 470 ohms (×6): Current-limiting resistors connected in series with each segment of the 7-
segment displays to protect the LEDs from excessive current.
 470 kilo-ohms (×2): Timing resistors used in the 555 Timer circuit to set the frequency
of the clock pulse.

6. Capacitor – 1.5μF (×1)

 Function: Used in combination with resistors in the 555 timer circuit to define the
oscillation frequency.
 Role in Circuit: Controls the timing interval of the pulse output (1 second pulse width).

7. 9V Battery or DC Power Supply

 Function: Supplies power to the circuit components.

 Role in Circuit: Provides the necessary operating voltage for the ICs and displays.
Circuit Description
The circuit of the 6-digit digital clock is designed using a modular and sequential approach, in
which each block of the circuit handles a specific digit of the time (seconds, minutes, or hours).
The primary elements of the design include a clock generator, decade counters, display units,
and logic gates for reset control and digit overflow management.

555 Timer as Clock Generator

The 555 Timer IC is configured in astable mode, which allows it to generate a continuous
stream of square wave pulses. The frequency of the output signal is determined by the values of
two resistors and one capacitor connected to the 555:

 Two resistors (470kΩ) and a capacitor (1.5μF) are connected to Pins 6, 7, and 2.
 Pin 3 is the output pin, which delivers a 1 Hz pulse (one pulse per second).
This pulse acts as the time base of the digital clock and is fed into the first counter
(CD4026).

CD4026 ICs for Digit Counting

A total of six CD4026 ICs are used in the design. Each one is responsible for a single digit on
the 6-digit display:

 U7 and U6: Count seconds (from 00 to 59)

 U5 and U4: Count minutes (from 00 to 59)
 U3 and U1: Count hours (from 00 to 23)

Each CD4026 IC:

 Receives a clock input at Pin 1.

 Drives a 7-segment display directly through its segment outputs (Pins 10–7, 6, 11, 9).
 Sends a carry-out signal through Pin 5 when it rolls over from 9 to 0, which is used to
increment the next digit.

This cascading arrangement allows the six ICs to form a full HH:MM:SS format.

Reset and Overflow Management using AND Gates (IC 7411)

To ensure that the counters do not exceed their logical limits (i.e., seconds and minutes should
reset at 60, hours should reset at 24), logic gates are introduced:

 The 7411 IC, which contains three 3-input AND gates, is used to detect when specific
combinations are reached (like 6 or 3 on a digit).
  For example, when the seconds count reaches “60” (i.e., units = 0 and tens = 6), the AND
gate detects this and triggers a reset on both second counters, while also sending a clock
pulse to the minute counter.
 A similar logic applies to minutes (reset at 60) and hours (reset at 24).

7-Segment Displays

Each CD4026 directly drives a common cathode 7-segment display. The displays show
numeric values from 0 to 9. To prevent the segments from drawing excessive current, 470Ω
resistors are connected in series with each segment line.

Power Supply

The entire circuit is powered using a 9V battery or a DC adapter. The components selected
operate comfortably within this voltage range.

Flow Summary:

1. 555 Timer generates 1-second pulses.

2. Pulses enter the first CD4026, which counts 0–9 and drives the units digit of seconds.
3. On roll-over, a carry-out pulse is sent to the tens digit of seconds.
4. When 60 seconds is detected via AND gates, a reset occurs and the minute counters
increment.
5. The same process continues for minutes and hours, with control logic ensuring that
minutes reset at 60 and hours reset at 24.
Working Principle
The operation of the 6-digit digital clock is based on sequential counting logic, where each
stage of the circuit is responsible for measuring and displaying a specific portion of time:
seconds, minutes, and hours. The system works synchronously, relying on a central timing
pulse and cascading logic to ensure accurate counting and time formatting.

1. Pulse Generation by the 555 Timer

The circuit starts with a 555 Timer IC configured in astable mode. This configuration makes
the timer produce a continuous stream of square wave pulses at a regular interval. By choosing
appropriate resistor and capacitor values (470 kΩ resistors and a 1.5 μF capacitor), the timer is
tuned to generate pulses at 1 Hz frequency, i.e., one pulse per second.

 Each pulse represents 1 second in real-time.

 The output pulse is available at pin 3 of the 555 timer.
 This output is connected to the clock input (pin 1) of the first CD4026 counter.

2. Counting Seconds with CD4026 ICs

The first two CD4026 ICs (U7 and U6) are used to count seconds:

 U7 handles the units digit (0–9) of seconds.

 U6 handles the tens digit (0–5) of seconds.

Each time the 555 timer sends a pulse:

 U7 increments its count.

 Once U7 reaches 9 and receives the next pulse, it resets to 0 and generates a carry-out
signal on pin 5, which goes to the clock input of U6.

Thus, for every 10 seconds counted by U7, U6 increments by 1.

When U6 reaches 6 (i.e., when the seconds hit 60), the system must:

 Reset U6 and U7 back to 00.

 Send a clock pulse to the minute counter (U5).

To perform this logic, a 3-input AND gate (from IC 7411) is used. The gate detects when U7 =
0 and U6 = 6, and then triggers a reset and carry to the next stage.

3. Counting Minutes and Hours

The same logic applies to the minutes:

  U5: units digit (0–9)
 U4: tens digit (0–5)
When the minute digits reach 60 (i.e., U4 = 6), another AND gate detects this and:
 Resets U5 and U4.
 Sends a clock pulse to the hour counter (U3).

For the hours, which range from 00 to 23:

 U3: units digit (0–9)

 U1: tens digit (0–2)
Another AND gate detects the "24-hour" condition (i.e., U1 = 2 and U3 = 4) and:
 Resets both hour counters to 00.

This ensures the clock wraps correctly from 23:59:59 back to 00:00:00.

4. Display Output

Each CD4026 is connected to a common cathode 7-segment display, which it drives directly
using its internal decoding logic. The CD4026 converts the count into a 7-segment pattern
without the need for an external decoder.

 The segments are connected through 470Ω resistors to limit current.

 The display shows real-time counting, progressing smoothly from 00:00:00 to 23:59:59.

System Behavior Summary:

Time Unit Counter ICs Max Count Trigger to Next Unit Reset Condition
Seconds U7 & U6 59 U6 = 6 U7 = 0 & U6 = 6
Minutes U5 & U4 59 U4 = 6 U5 = 0 & U4 = 6
Hours U3 & U1 23 U1 = 2 & U3 = 4 U3 = 0 & U1 = 0

This design reflects a synchronous and modular approach to digital timekeeping. By chaining
CD4026 counters and controlling overflow with 7411 AND gates, the system maintains accurate
time format using only basic digital ICs, no microcontroller or complex programming required.
Gate and IC Operation
This section breaks down the behavior and function of each critical component used in the digital
clock, especially the integrated circuits (ICs) that form the core of its logic and timing systems.
The proper selection and interconnection of these components ensure correct time progression
and digit display.

7.1. 555 Timer IC

The 555 Timer is a versatile IC that can operate in monostable, bistable, or astable modes. In
this project, it is configured in astable mode to generate continuous clock pulses.

🔧 Technical Behavior:

 It produces a square wave with a consistent frequency determined by:

f=1.44(R1+2R2)×Cf = \frac{1.44}{(R1 + 2R2) \times C}f=(R1+2R2)×C1.44

 With R1, R2 = 470 kΩ and C = 1.5 μF, the output frequency is approximately 1 Hz,
giving one pulse per second.
 Pin 3 outputs the pulse and is connected to the clock input of the first CD4026.

🧠 Role in Circuit:

 Acts as the “heartbeat” of the system.

 Provides synchronized timing for all subsequent counting stages.
 Ensures consistent real-time second-by-second progression.

7.2. CD4026 IC (Decade Counter and Display Driver)

The CD4026 is a 16-pin CMOS IC that combines a decade counter (0–9) and a 7-segment
decoder/driver. This IC eliminates the need for separate BCD counters and display decoders.

🔌 Important Pins:
Pin Function

1 Clock Input (CLK)

Pin Function

3 Display Enable (DE)

5 Carry Out (CO)

15 Reset (RST)

10–7, 6, 11, 9 Segment Outputs (A–G)

⚙️Operation:

 Each rising edge on pin 1 increments the count.

 The count is automatically decoded into 7-segment display outputs.
 When the count goes from 9 → 0, pin 5 (CO) goes high for one clock cycle, acting as a
carry signal to the next CD4026.
 Pin 15 (RST) can be used to reset the count to 0 when driven HIGH.

📌 Use in Project:

 Six CD4026 ICs are used, each driving one digit of the clock (Seconds, Minutes, Hours).
 The cascading of CD4026s creates a seamless count progression from 00:00:00 to
23:59:59.
 Segment pins are directly wired to the 7-segment displays.

7.3. IC 7411 – Triple 3-Input AND Gate

The IC 7411 contains three independent 3-input AND gates, which output HIGH only when
all three inputs are HIGH. It’s a TTL device used for logic condition detection.

🔧 Truth Table (Simplified for 1 Gate):

A B C Output

0 0 0 0

1 1 0 0

1 1 1 1
📌 Application in This Clock:

 AND gates monitor specific bit combinations on the outputs of CD4026s.

 When a condition like seconds = 60 (i.e., U6 = 6 and U7 = 0) is detected, the AND gate:
o Sends a HIGH signal to reset the seconds.
o Sends a clock pulse to increment the minute counter.

🧠 Example:

 U8C monitors seconds. When:

o U7 = 0 (units = 0)
o U6 = 6 (tens = 6)
o Output of AND gate = HIGH
→ Resets seconds and increments minutes.
 Similar logic is applied to minutes (reset at 60) and hours (reset at 24).

Integration of All Components

The operation of these components is interdependent:

 The 555 Timer starts the counting process.

 CD4026 ICs count and display time, propagating carry pulses.
 7411 AND gates observe specific states and enforce correct time formatting through
logic-based resets and transitions.

Each stage is synchronized, and the modular design means that any digit can be debugged or
modified without affecting the entire system.
Simulation results
Conclusion
This project successfully demonstrates the design and implementation of a 6-digit digital clock
using fundamental digital logic components — without the need for microcontrollers or
programming. The final system counts and displays time in a HH:MM:SS format, ranging from
00:00:00 to 23:59:59, and performs accurate time progression using cascaded CD4026
counters, a 555 timer, and 7411 AND gates.

Through this project, we were able to:

 Apply theoretical knowledge of sequential logic, counters, and logic gates to a real-
world application.
 Understand the behavior and usage of key ICs like the 555 Timer (for pulse generation),
CD4026 (for counting and display), and IC 7411 (for logic-based overflow detection).
 Gain practical experience in designing modular and scalable digital systems.
 Simulate, test, and validate the behavior of the system using appropriate simulation tools.

The project highlights how a modular design approach — using individual counters for each
digit and logic gates for managing transitions — leads to a robust and predictable timekeeping
system. It also reinforces the importance of clock synchronization, carry propagation, and
reset logic in the design of complex digital circuits.

While today’s digital clocks are typically implemented with microcontrollers and software, this
hardware-based approach offers a transparent view into the inner workings of digital
systems. It helps students develop a deeper appreciation for digital electronics and strengthens
their problem-solving skills in circuit design.

This project not only met all its functional objectives but also served as a valuable educational
experience in the field of Digital Logic Design (DLD).