By Getachew Teshome
Addis Ababa University, Department of Electrical and
Computer Engineering
The heart of a computer is the
CPU (Central Processing Unit)
Memory
Output
CPU IOP Input
CPU performing arithmetic and logic operations,
writing to and reading from memory,
Memory storage of instructions and data to be
processed.
IOP receives data from input devices and sends data
to output devices.
Each instruction guides the CPU what to do in the
coming clock cycle.
It specifies
The operation to be performed,
Source operands, if any, on which the operation is to be
performed.
Destination operand where the result of the
operation, if any, is to be performed.
Instruction mode that is a modifier to the operation.
load R4, &16 0001 0100 00001000
add R2, R1, R3 0110 0010 0001 0011
Load
R0 Store
R1 Add
Sub
R2
Mult
R3 Div
Jz
Instruction Decoder
Arithmetic & Logic Unit (ALU)
Register File
Instruction Register
R0
R1
R2
PC
R3
Instruction
Fetch and
Memory
Decoder ALU
R14
R15
Register
File
CPU
Harvard Von Neuman
Data and Program are
Both data and
stored on separate program are stored
memory. on the same memory.
The two memories
Instruction fetching
can be accessed and data fetching
simultaneously. have to be carried out
on subsequent cycles.
Mem CPU
Program Data
Memory CPU Memory
ory
Application software
Compilers
ARCHITECTURE a.k.a. ISA (Instruction Set Architecture)
- Platform-specific
- a limited set of assembly language commands "understood
by hardware (e.g. ADD, LOAD, STORE, RET)
The hw/sw
divide
MICROARCHITECTURE (Hardware implementation of the ISA)
- Pentium IV implements the x86 ISA
- Motorola G4 implements the Power PC ISA
Circuits
Devices
EECS 370: Introduction to
Computer Organization Prof. V. Bertaco et al 10/35
The University of Michigan
Improvement
New Architectures for specific purpose
processors (Embedded Systems).
The first step in design is Instruction Set
Architecture (ISA).
Number of Instructions.
Types of Instructions
Size of Instructions
What instructions?
Function - add, sub, mult, inc
Flow control - jz, ret,
Storage - ld, st
Number of operands
1, 2, 3 operands
Operand range?
Memory size
Register count
opcode Operand 1
Opcode Operand 1 Operand 2
Opcode Operand 1 Operand 3 Operand 4
Addressing modes
Immediate
Register
Register Direct
Memory Indirect
Displacement
PC relative
Consider the following C code and generate the
corresponding machine code.
int a, b, c; Machine A Machine A
a=0; & 10,14,18 & 10,14,18
a=a+1; sti 10, 0; cpi r0, 0;
Ld r1, 10; st 10, r0;
b=a; Addi r1, r1, 1; Ld r1, 10;
St 10, r1 Inc r1;
Ld r2, 10; St 10, r1
St 14, r2 Ld r2, 10;
St 14, r2
MIPS
32 registers ( $0 - $31 )
32 bits in each register (called a word in MIPS-speak)
Intel x86
4 general purpose registers (eax, ebx, ecx, edx) 32 bits
You can treat them as two 8 or one 16-bits as well (ah, al, and ax)
Special registers: 3 pointer registers (si,di,ip), 4 segment
(cs,ds,ss,es),
2 stack (sp, bp), status register (flags)
LC-2K8 (the architecture you will be simulating)
8 registers, 32 bits each
EECS 370: Introduction to Computer Organization Prof. V. Bertaco et al
The University of Michigan 17/35
