EMT 353/3 DIGITAL IC DESIGN

VERILOG BEHAVIOURAL
MODELING
(Part 4)

| SCHOOL OF MICROELECTRONIC ENGINEERING | UniMAP

 State Encoding Techniques

 Binary Encoding
 Assigns states by the minimum logic difference
in the state transition graph.
 This normally reduces the amount of logic needed
to decode each state.
 The minimum number of bits, n in the state
register for an FSM with m states is log m/log 2

00 01 10 11

Example: 4 states  2 bits used to represent each state

 State Encoding Techniques

 One Hot Encoding

 Its principle is to associate one code bit and also
one flip-flop to each state.
 At a given clock cycle during operation, one and
only state variable is asserted. Only two state
variables toggle during a transition between two
states.

0001 0010 0100 1000

Example: 4 states  4 bits used to represent each state

 State Encoding Techniques

 One Hot Encoding (cont..)

 One-hot encoding is very appropriate with most FPGA
targets where a large number of flip-flops are available.
 It is also a good alternative when trying to optimize
speed or to reduce power dissipation.
 State Encoding Techniques

 Gray Code Encoding

 Gray encoding guarantees that only one state variable
switches between two consecutive states.
 It is appropriate for controllers exhibiting long paths
without branching. In addition, this coding technique
minimizes hazards and glitches.
 Very good results can be obtained when implementing
the state register with T flip-flops.

00 01 11 10

Example: 4 states  2 bits used to represent each state

 State Encoding Techniques

Example: State encoding for 8 states

BINARY GRAY ONE-HOT

B 2B 1B 0 G2G1G0 O7O6O5O4O3O2O1O0
000 000 00000001
001 001 00000010
010 011 00000100
011 010 00001000
100 110 00010000
101 111 00100000
110 101 01000000
111 100 10000000
 PRE-LAB 2 TASK

Design an FSM-based 3-bit binary counter using

Verilog HDL which is able to count-up from 3’d0
to 3’d7 and repeats.

Assume that the binary counter counts at every

positive edge CLK with asynchronous RESET
and the start counting sequence is 000.

Design, simulate and verify the design from the

generated simulation waveform.
module count7 (
input clk, rst,
output reg [2:0] count);

always @ (posedge clk)

begin
if (rst | (count ==3’d7))
count = 0;
else
count = count + 1;
end
endmodule
LAB 2 TASK (DISCUSSION)
 Example A
Mealy Sequence
Detector:
Detects two
successive 0's or 1's
(..00.. or ..11..)
in serial bit stream
module seq_det_mealy_1exp (clock, reset, in_bit, out_bit);
input clock, reset, in_bit;
output out_bit;
reg [2:0] state_reg, next_state;

parameter start_state = 3'b000; Separate behaviours for

parameter read_1_zero = 3'b001;
each state, nextstate
parameter read_1_one = 3'b010;
parameter read_2_zero = 3'b011; transition and output
parameter read_2_one = 3'b100; assignment

always @ (posedge clock or posedge reset) // state

if (reset == 1) state_reg <= start_state; else state_reg <=
next_state;

always @ (state_reg or in_bit) // nextstate

case (state_reg)
start_state: if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
read_1_zero: if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
 read_2_zero: if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
read_1_one: if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;
else next_state <= start_state;
read_2_one: if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;
else next_state <= start_state;
default: next_state <= start_state;
endcase

assign out_bit = (((state_reg == read_2_zero && in_bit == 0 )) ||

((state_reg == read_2_one) && in_bit == 1)) ? 1 : 0;
// output
endmodule // written using style 2

NOTE: Output asserts after two consecutive matching inputs.

Again, machine is a Mealy type.
 More examples..

Example B
 module seq1011( clk, rst, inp, outp);
input clk, rst, inp;
output outp;

reg [1:0] state;

reg outp;

always @ (posedge clk or posedge rst)

begin
if (rst) state <= 2'b00;
else
begin
case (state)
2'b00: begin
if( inp ) state <= 2'b01;
state & nextstate else state <= 2'b10;
transition is embed into a end
single behaviour 2'b01: begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
 2'b10: begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b11: begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end

always @(posedge clk or posedge rst)

begin
if( rst ) outp <= 0; else
Separate behaviour block
if( state == 2'b11 ) outp <= 1;
for output
else outp <= 0;
end
endmodule // FSM coding style 3
 Another example..

Example C

ASM Chart: Up-down Counter

 Explicit FSM Up-down Counter

module Up_Down_Explicit (count, up_dwn, clock, reset_);

output [2:0] count;
input [1:0] up_dwn;
input clock, reset_;
reg [2:0] count, next_count;

always @ (negedge clock or negedge reset_)

if (reset_ == 0) count = 3’b0;
else count = next_count;

always @ (count or up_dwn) begin

case (count)
0: case (up_dwn)
0, 3 : next_count = 0;
1 : next_count = 1;
2 : next_count = 3'b111;
default next_count = 0; endcase
 1: case (up_dwn)
0, 3: next_count = 1;
1: next_count = 2;
2: next_count = 0;
default next_count = 1; endcase
2: case (up_dwn)
0, 3: next_count = 2;
1: next_count = 3;
2: next_count = 1;
default next_count = 2; endcase
3: case (up_dwn)
0, 3: next_count = 3;
1: next_count = 4;
2: next_count = 2;
default next_count = 3; endcase
4, 5, 6, 7: if (up_dwn == 0 || up_dwn == 3) next_count = count;
else if (up_dwn == 1) next_count = count + 1;
else if (up_dwn == 2) next_count = count –1;
else count = 0;
endcase
end
endmodule
 Implicit FSM Up-down Counter

module Up_Down_Implicit1 (count, up_dwn, clock, reset_);

output [2:0] count;
input [1:0] up_dwn;
input clock, reset_;
reg [2:0] count;

always @ (negedge clock or negedge reset_)

if (reset_ == 0) count = 3’b0; else
if (up_dwn == 2’b00 || up_dwn == 2’b11) count = count; else
if (up_dwn == 2’b01) count = count + 1; else
if (up_dwn == 2’b10) count = count –1;
endmodule
 Try this..

 Design a FSM of an even parity generator with

following specifications:
 Asynchronous reset is used
 Bit_in is clocked on rising edge
 Even parity will be asserted if an odd number of 1’s
have been received
 Use Moore machine FSM to represent the design
clk reset
Block diagram

Bit_in Par_Gen Detect