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Assignment 1 | PDF | Field Effect Transistor | Mosfet
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Assignment 1

The document contains 10 multiple choice questions about MOSFET devices and CMOS inverters. Question topics include: removing body effect in n-channel MOSFETs by connecting the substrate to the most negative bias; the relationship between drawn channel length and effective channel length accounting for diffusion length; the behavior of a saturated n-channel MOSFET accounting for channel length modulation; the effect of drain induced barrier lowering on operating frequency; the depletion region behavior under gradual channel approximation; the unit of mobility; the drain current equation used in SPICE level-2 accounting for channel length modulation; the switching threshold of a static CMOS inverter with symmetric pull-up and pull-down networks; and the state of the NMOS

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Jayamani Krishnan
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297 views3 pages

Assignment 1

The document contains 10 multiple choice questions about MOSFET devices and CMOS inverters. Question topics include: removing body effect in n-channel MOSFETs by connecting the substrate to the most negative bias; the relationship between drawn channel length and effective channel length accounting for diffusion length; the behavior of a saturated n-channel MOSFET accounting for channel length modulation; the effect of drain induced barrier lowering on operating frequency; the depletion region behavior under gradual channel approximation; the unit of mobility; the drain current equation used in SPICE level-2 accounting for channel length modulation; the switching threshold of a static CMOS inverter with symmetric pull-up and pull-down networks; and the state of the NMOS

Uploaded by

Jayamani Krishnan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment-1

Q1. In order to remove the body effect, the substrate of an n-channel enhancement mode
MOSFET should be:

(a) Connected to the most positive bias


(b) Connected to the most negative bias
(c) Grounded
(d) Floating
Answer: (b)

Q2. Assuming that the bulk NMOS device has equal source and drain doping then the effective
channel length (Leff) is related to drawn length (Ldrawn) and diffusion length (LD) as :

(a) Leff = Ldrawn – 2 LD


(b) Leff = Ldrawn – LD
(c) Leff = 2Ldrawn – LD
(d) Leff = LD – Ldrawn
Answer: (a)

Q3. A bulk n-channel enhancement mode MOSFET is biased in the saturation region of
operation, such that VDS> VGS – Vth. Vthis the threshold voltage. Taking into consideration
Channel Length Modulation, the MOSFET in saturation state behaves as a:

(a) Constant Voltage Source


(b) Variable Voltage Source
(c) Current Source with infinite output impedance
(d) Current Source with finite output impedance.
Answer: (d)

Q4. Drain Induced Barrier Lowering (DIBL) for a bulk MOSFET

(a) Reduces the device operating frequency


(b) Increases the device operating frequency
(c) Has no influence on the device operating frequency
(d) Increases the carrier transit time
Answer: (a)
Q5. Under Gradual Channel Approximation (GCA), the depletion region in the bulk of the long
channel MOSFETon application of a drain bias
(a) Reduces as we move towards the drain end
(b) Increases as we move towards the drain end
(c) Remains constant
(d) Has no relationship
Answer: (b)

Q6. The unit of mobility is:


(a) m2/V-s
(b) m/V2-s
(c) m/V-s2
(d) m/V-s
Answer: (a)

Q7. The formulation used for drain current in SPICE Level-2 for MOSFET is given as:
(a) ID = IDsat[1 / (1-λ VDS) ]
(b) ID = IDsat[1 / (1-VDS) ]
(c) ID = IDsat[λ / (1-λ VDS) ]
(d) ID = IDsat[λ / (λ -λ VDS) ]
Where λ is the CLM parameter
Answer: (a)

Q9. A static CMOS Inverter is powered by a supply voltage of VDD. Assuming the pull-up and
pull-down networks are equal and symmetric, which of the following statement are true:
(a) The switching threshold is VDD/2
(b) The switching threshold is 2VDD
(c) The switching threshold is VDD
(d) The switching threshold is VDD/4
Answer: (a)

Q10. For a static CMOS, the output is high, then the state of the NMOS and PMOS are as
follows:
(a) NMOS on and PMOS non-linear
(b) NMOS off and PMOS linear
(c) NMOS off and PMOS non-linear
(d) NMOS on and PMOS linear
Answer: (b)

Note: Question #8 will not consider in evaluation.

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