Basic Logic Design with Verilog HDL
Combinational Circuits
Lecture note ver.1 by Chen-han Tsai ver.2 by Chih-hao Chao ver.3 by Xin-Yu Shi ver.4 by Bo-Yuan Peng ver.5 by Cheng-Zhou Zhan
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
What is Verilog HDL?
Why using Hardware Description Language?
Design abstraction: HDL layout by human Hardware modeling Reduce cost and time to design hardware
Two Popular HDLs
VHDL Verilog
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What is Verilog HDL?
Key features of Verilog
Supports various levels of abstraction
Behavior level Register transfer level Gate level Switch level
Simulate design functions
Different Levels of Abstraction
Architectural / Algorithmic Level
Implement a design algorithm in high-level language constructs.
Register Transfer Level
Describes the flow of data between registers and how a design process these data.
Different Levels of Abstraction
Gate Level
Describe the logic gates and the interconnections between them.
Switch (Transistor) Level
Describe the transistors and the interconnections between them.
Simplified Hardware Design Flow
Designer
Level RTL Simulation RTL Editor
RTL Code
Cost Low
High
Verilog
Gate Level Simulation
Logic Synthesizer
Gate Level Code
Post Gate Level Simulation
Place & Route
Physical Layout
Tape Out
Low
High
Chip
Example: 1-bit Multiplexer
to select output
sel 0 out 1
sel 0 0 0 0 1
in1 0 0 1 1 0 0 1 1
in2 0 1 0 1 0 1 0 1
out 0 0 1 1 0 1 0 1
in1 in2
if (sel==0) out = in1; else out = in2;
1 1 1
out = (selin1) + (selin2)
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Gate Level Description
in1 in2
n1
iv_sel
a1 a2
a1_o
o 1
out
a2_o
sel
iv_sel
Gate Level: you see only netlist (gates and wires) in the code.
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Behavior Level / RTL Description
always block
assign
RTL: you may see high level behavior in the code
Behavior: event-driven behavior description construct
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
12
A Simple Verilog Code
module name declaration syntax in/out port
port/wire declaration
kernel hardware gate-connection/ behavior
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Module
Basic building block in Verilog Module
1. Created by declaration (cant be nested) 2. Used by instantiation
Interface is defined by ports May contain instances of other modules All modules run concurrently
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Module Instantiation
Adder
instance example
Adder
Adder
Adder_tree
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Instances
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters and I/O interface.
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Analogy: Module vs. Class
Format
module m_Name( IO list ); ... endmodule class c_Name { ... };
Instantiation
Member Hierachy
m_Name ins_name ( port connection list );
ins_name.member_signal
c_Name obj_name;
obj_name.member_data
instance.sub_instance.membe object.sub_object.member_data r_signal
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Port Connection
Connect module port by order list
FA1 fa1(c_o, sum, a, b, c_i);
Connect module port by name (Recommended)
Usage: .PortName (NetName)
FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));
Not fully connected
FA1 fa3(c_o, , a, b, c_i);
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Verilog Language Rule
Case sensitive Identifiers
Digits 0123456789 Underscore _ Upper and lower case letters from the alplabet
Terminate statement/declaration with semicolon ; Comments
Single line: // its a single line comment example Multi-line: /* When the comment exeeeds single line, multi-line comment is necesssary */
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Data Type: Register
Register
Keyword: reg, integer, time, real Event-driven modeling Storage element (modeling sequential circuit) Assignment in always block (LHS of expressions)
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Data Type: Net
Net
Keyword: wire, wand, wor, tri, triand, trior, supply0, supply1 Doesnt store value, just a connection Input, output and inout ports are default wire
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Four-valued Logic Value
Nets and registers in Verilog codes hold four-valued data
0 represent a logic 0 or false condition 1 represent a logic 1 or true condition z
Output of an undriven tri-state driver High-Z value Models case where nothing is setting a wires value
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Four-valued Logic Value
Nets and registers in Verilog codes hold four-valued data
x
Models when the simulator cant (doesnt) decide the value un-initialized or unknown logic value
Initial state of registers A wire is being driven to 0 and 1 simultaneously Output of a gate with z inputs
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Logic System
Four values: 0, 1, x/X, z/Z (not case sensitive)
The logic value x denotes an unknown (ambiguous) value The logic value z denotes a highimpedance value (High-Z value)
Primitives have built-in Logic Simulators describe 4-value logic
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Logic System: Example
a b a
0 1 x
0 0 1 0 0
1 0 1
X 0 X
Z 0 X
X
Z
0
0
X
X
X
X
X
X
b y
x z
x z
x z
x z
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Number Representation
Format: <size><base_format><number> <size> - decimal specification of bits count
Default: unsized and machine-dependent but at least 32 bits
<base_format> - ' followed by arithmetic base of number
d or D decimal (default if no base format given) h or H hexadecimal o or O octal b or B binary
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Number Representation
Format: <size><base_format><number> <number> - value given in base of base format
_ can be used for reading clarity x and z are automatically extended
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Number Representation
Examples:
6b010_111 8b0110 4bx01 16H3AB 24 5O36 16Hx 8hz gives 010111 gives 00000110 gives xx01 gives 0000001110101011 gives 00011000 gives 11110 gives xxxxxxxxxxxxxxxx gives zzzzzzzz
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Number Representation
659 // unsized decimal h 837ff // unsized hexadecimal o7460 // unsized octal 4af // illegal syntax 4b1001 // 4-bit binary 5D 3 // 5-bit decimal 3b01x // 3-bit number with unknown LSB 12hx// 12-bit unknown 8d -6 // illegal syntax -8d 6 // phrase as - (8d6)
// underline usage 27_195_000 16b0001_0101_0001_1111 32h12ab_f001 // X and Z is sign-extended reg [11:0] a; initial begin a = hx; a = h3x; a = h0x; end
// yields xxx // yields 03x // yields 00x
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Net Concatenation
Module B
Module A
3o7
Representations {b[3:0],c[2:0]} {a,b[3:0],w,3b101} {4{w}} {b,{3{a,b}}} Meanings
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1} {w,w,w,w} {b,a,b,a,b,a,b}
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Module C
Operators
Arithmetic Operators Relational Operators Equality Operators Logical Operators Bit-wise Operators Unary Reduction Shift Operators Conditional Operators Concatenations +, -, *, /, % <, <=, >, >= ==, !=, ===, !== !, &&, || ~, &, |, ^, ~^ &, ~&, |, ~|, ^, ~^ >>, << ?: {}
31 Excerpts from CIC training course: Verilog_9807.pdf
Operator Examples
All bits are 0 logic false
32 Excerpts from CIC training course: Verilog_9807.pdf
Compiler Directives
'define
'define RAM_SIZE 16 Defining a name and gives a constant value to it.
'include
'include adder.v Including the entire contents of other verilog source file.
'timescale
'timescale 100ns/1ns Setting the reference time unit and time precision of your simulation.
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System Tasks
$monitor
$monitor ($time,"%d %d %d",address,sinout,cosout); Displays the values of the argument list whenever any of the arguments change except $time.
$display
$display ("%d %d %d",address,sinout,cosout); Prints out the current values of the signals in the argument list
$finish
$finish Terminate the simulation
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
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Gate Level Modeling
Steps
Develop the Boolean function of output Draw the circuit with logic gates/primitives Connect gates/primitives with net (usually wire)
HDL: Hardware Description Language
Figure out architecture first, then write code.
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Primitives
Primitives are modules ready to be instanced Smallest modeling block for simulator Verilog build-in primitive gate
and, or, xor, nand, nor, xnor
prim_name #delay inst_name( out0, in0, in1,.... );
not, buf
prim_name #delay inst_name( out0, out1, ..., in0);
User defined primitive (UDP)
building block defined by designer
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Case Study: Full Adder
Ci A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Co 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1
0 0
Co
Full Adder S
Ci
0 0 1 1 1 1
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Case Study: Full Adder
Co = AB + BCi + CiA
A B B Ci Ci A
Co
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Case Study: Full Adder
a b c sum
sum = a b ci
a b c
sum
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Case Study: Full Adder
Full Adder Connection
Instance ins_c from FA_co Instance ins_s from FA_sum
a b b c c a full adder carry out connection co
a b c
sum connection sum
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
42
Test Methodology
Systematically verify the functionality of a model. Procedure of simulation
Detect syntax violations in source code Simulate behavior Monitor results
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Test Methodology
Stimulus
Testbench
Hardware Design (Design Under Test)
Response
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Verilog Simulator
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Testbench for Full Adder
module t_full_add(); reg a, b, cin; wire sum, c_out; // for stimulus waveforms
full_add M1 (sum, c_out, a, b, cin); //DUT initial #200 $finish; // Stopwatch = = = = = = = =
initial begin #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = end endmodule
0; 1; 0; 1; 0; 1; 0; 1;
cin cin cin cin cin cin cin cin
// Stimulus patterns 0; // Execute in sequence 0; 0; 0; 1; 1; 1; 1;
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Summary
Design module / DUT
Divide-and-Conquer Architecture figure of each sub-module Create hardware design in gate-level or RT-level Connection of sub-modules
Make architecture figures before you write Verilog codes
Partition the whole design into several parts
Test-bench
Feed input data and compare output values at right timing slots Usually describe in behavioral level Not real hardware, just like software programming (e.g. C/C++)
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Note
Verilog is a platform
Support hardware design (design module) Also support C/C++ like coding (test bench)
How to write verilog well?
Know basic concepts and syntax Get a good reference codes (a person or some code files) Form a good coding style
Hardware
Combinational circuits (todays topic) Sequential circuits (we wont model them in this course)
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions
49
Start to Use ModelSim
Double click the icon ModelSim SE 5.7d
Start to Use ModelSim
Create a Project
Assign by yourself
Open a New File
Edit Verilog Files
Save files as xxxxx.v
Edit your verilog file here
Add Files to Project
Add Files to Project
Your design
Your testbench
Add Files to Project
Compile
Your design Your testbench
Compile Successful Message
Simulation
2. Press Simulate
1. Choose your design
Simulation
1. Choose your testbench
2. Press OK
Simulation
View Signals
View Signals
View Signals
View Signals
Run
End Simulation
