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8051 Architecture

The 8051 architecture was developed by Intel in the 1980s using NMOS and later CMOS technology. It has 128 bytes of RAM, 4K bytes of ROM, two timers, serial port, and four 8-bit I/O ports. The CPU contains an ALU and CU to control operations. Program memory stores instructions, data memory stores variables, and I/O ports connect to external devices. A crystal oscillator provides the clock signal. Newer variants include larger memory, USB, encryption, ADCs, and wireless modules.

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Leonard Valdez
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278 views17 pages

8051 Architecture

The 8051 architecture was developed by Intel in the 1980s using NMOS and later CMOS technology. It has 128 bytes of RAM, 4K bytes of ROM, two timers, serial port, and four 8-bit I/O ports. The CPU contains an ALU and CU to control operations. Program memory stores instructions, data memory stores variables, and I/O ports connect to external devices. A crystal oscillator provides the clock signal. Newer variants include larger memory, USB, encryption, ADCs, and wireless modules.

Uploaded by

Leonard Valdez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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8051 Architecture

8051 Architecture

Richard Myrick T. Arellaga

Urdaneta City University


8051 Architecture

Introduction

Developed by Intel in the mid 80’s


Also known as Intel MCS-51
Instruction set Architect was John
Wharton
Developed using N-type
metal-oxide-semiconductor
Later versions used Complementary
Metal Oxide Semiconductor
(CMOS)
8051 Architecture

Specifications

RAM 128 bytes


ROM 4K bytes
Timer 2 - 16bit timer
Serial 1 Serial port
I/O 4 I/O Port each 8 bit wide
Bus 8-bit Data Bus, 16-bit Address
8051 Architecture

Block Diagram
8051 Architecture

Central Processing Unit (CPU)

Heart of the System


Mainly contains ALU and CU
8051 Architecture

ALU and CU

Arithmetic Logic Unit(ALU) - Responsible in Arithmetic and


Logic Operations
Control Unit (CU) - Responsible for all the timing of
communications between CPU and peripherals
8051 Architecture

Program Memory

Also known as code memory


Retains data even if power is removed
8051 Architecture

Data Memory

Also known as Random Access Memory


Responsible in storing values of variable temporary data and
immediate result for the proper operation of the MCU.
8051 Architecture

Data Memory

Generally volatile, data is loss when power is loss


Arranged as a Register and User accessible locations.
8051 Architecture

Input/Output (I/O) Ports

Provide connection to the outside world.


Can be configured as an input port or output port.
8051 Architecture

Input/Output (I/O) Ports

Provide gateway for passing data from the outside world using
sensors.
Output Ports allow the microcontroller to control external
devices such as motor, LED and other actuators.
8051 Architecture

Oscillator

Used to generate clock signal


Clock allows the operation of the MCU in synchronous
manner.
Usually in the form of Crystal Oscillator
8051 Architecture

Timer Peripheral

Used to generate delay


Can count external event thru T0 and T1 pin
8051 Architecture

Serial Port

Used to communicate to other serial devices such as a PC


can be used to communicate wirelessly thru another wireless
serial device thru bluetooth,Zigbee and other wireless
communication protocol/devices.
8051 Architecture

Interrupt Control

Used to control internal and external interrupt event of the


8051.
8051 Architecture

System Bus

Data Memory, Program Memory, I/O Ports, Timers, Interrupt


Controller and CPU are interfaced together thru the System
Bus.
8051 Architecture

New and advance 8051 Devices

Newer 8051 devices may contain


Larger memory
USB
AES and DES Encryption
Analog to Digital Converter
Analog Comparator
Op-amps
RF module and others

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