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3.5 Instruction Formats: Three-Address Machines

This document discusses instruction formats used in computer processors. It explains that instructions typically contain an opcode and operands to specify where values come from and go to. There are four categories of instruction formats: zero-address, one-address, two-address, and three-address. Zero-address machines assume operand locations are default, one-address machines use accumulators, two-address machines use one address for source and result, and three-address machines separate source operands and result. RISC processors typically use three addresses while CISC processors typically use two addresses.

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لطيف احمد حسن
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119 views4 pages

3.5 Instruction Formats: Three-Address Machines

This document discusses instruction formats used in computer processors. It explains that instructions typically contain an opcode and operands to specify where values come from and go to. There are four categories of instruction formats: zero-address, one-address, two-address, and three-address. Zero-address machines assume operand locations are default, one-address machines use accumulators, two-address machines use one address for source and result, and three-address machines separate source operands and result. RISC processors typically use three addresses while CISC processors typically use two addresses.

Uploaded by

لطيف احمد حسن
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Organization CoE234

3.5 Instruction Formats


 An instruction consists of an opcode, usually along with some additional information such
as:
 Where operands come from
 Where results go to
 The general subject of specifying where the operands come from and where results go to is
called addressing.
 Most recent processors use three addresses. However, it is possible to design systems with
two, one, or even zero addresses.
 There are four categories of instruction formats:
∗ 3-address instruction
Opcode Operand 1 Operand 2 Operand 3

∗ 2-address instruction
Opcode Operand 1 Operand 2

∗ 1-address instruction
Opcode Operand 1

∗ 0-address instruction
Opcode

 Operands may be registers or memory addresses.


 Three-address machines
∗ Two for the source operands, one for the result.
∗ RISC (Reduced Instruction Set Computer) processors use three addresses like ARM.
∗ Example:
ADD r1, r2, r3 ; r1= r2 + r3

17 |Page Prepared by: Dr. Dunia S.


Computer Organization CoE234
 Two-address machines
∗ One address doubles (for source operand & result).
∗ CISC (Complex Instruction Set Computer) processors use two addresses like core i9.

∗ Example:
ADD AX, BX ; AX=AX + BX
MOV EAX, EBX ; EAX EBX

 One-address machines
∗ In the early machines, when memory was expensive and slow, a special set of registers
was used to provide an input operand as well as to receive the result from the ALU. These
registers are called the accumulators.
∗ Instructions for these machines need to specify only the address of a single operand.
∗ There is no need to store the result in memory: this
– reduces the need for larger memory
– reduces the number of memory accesses ( speeds up the computation)
∗ Examples:
LDA P ; Load accumulator with P
ADD Q ; Add Q to accumulator
STA R ; Store accumulator in R
INC R1 ; Increment register R1 by 1
DEC R1 ; Decrement register R1 by 1
 Zero-address machines
∗ Locations of both operands are assumed to be at a default location.
∗ These machines use the stack as the source of the input operands and the result goes back
into the stack.

18 |Page Prepared by: Dr. Dunia S.


Computer Organization CoE234
∗ Examples:
NOP ; No operation
HLT ; Halt the CPU
PUSH operand ; Push operand into top of the stack
POP operand ; Remove the operand from top of the stack

Example: Evaluate the following expression:


Z= (A+B) * (C-D)
Using a) zero-address machines
b) one-address machines
c) two-address machines
d) three-address machines

Solution:
a)
PUSH A ; Push A onto stack
PUSH B ; Push B onto stack
ADD ; Pull the top two items of the stack, add them, and push A+B
on the stack
PUSH C ; Push C onto stack
PUSH D ; Push D onto stack
SUB ; Subtract top two items and push C-D on the stack

MUL ; Multiply top two items on the stack; that is (C-D) and (A+B)
and push the result
POP Z ; Pull the top item of the stack (the result)

19 |Page Prepared by: Dr. Dunia S.


Computer Organization CoE234
b)
LOAD A
ADD B
STORE Temp
LOAD C
SUB D
MUL Temp
STORE Z
c)
LOAD R1, A
ADD R1, B
LOAD R2, C
SUB R2, D
MUL R2, R1
STORE Z, R2
d)
ADD R1, A, B
SUB R2, C, D
MUL Z, R1, R2

20 |Page Prepared by: Dr. Dunia S.

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