MSI Circuits
Useful MSI circuits
▪ Four common and useful MSI circuits are:
❖ Decoder
❖ Demultiplexer
❖ Encoder
❖ Multiplexer
▪ Block-level outlines of MSI circuits:
decoder encoder
code entity entity code
mux data data demux output
input
select select
Decoders
▪ Convert binary
n
information from n input lines to
(max. of) 2 output lines.
▪ Known as n-to-m-linen decoder, or simply n:m or
nm decoder (m 2 ).
▪ May be used to generate 2 (or fewer) minterms of
n
n input variables.
Decoders
▪ Example: if codes 00, 01, 10, 11 are used to identify four
light bulbs, we may use a 2-bit decoder:
2x4
F0 Bulb 0
2-bit X Dec F Bulb 1
1
code Y
F2 Bulb 2
F3 Bulb 3
▪ This is a 24 decoder which selects an output line based on
the 2-bit code supplied.
▪ Truth table: X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Decoders
X Y F0 F1 F2 F3
▪ From truth table, circuit 0 0 1 0 0 0
for 24 decoder is: 0 1 0 1 0 0
1 0 0 0 1 0
▪ Note: Each output is a 2- 1 1 0 0 0 1
variable minterm (X'Y', F0 = X'Y'
X'Y, XY' or XY)
F1 = X'Y
F2 = XY'
F3 = XY
X Y
Decoders
▪ Design a 38 decoder by yourself.
Solution
Decoders
▪ In general, for an n-bit code, a decoder could select up to
2n lines:
n n
n-bit n to 2 up to 2
code : decoder : output lines
As n input generates 2^n output, which reminds us of
canonical SOP, thus a decoder can be used to generate
any function
Application of Decoder
• Example 1: Full adder circuit with decoder (3 x 8
decoder)
Demultiplexer
▪ Given an input line and a set of selection lines, the
demultiplexer will direct data from input to a selected
output line.
▪ An example of a 1-to-4 demultiplexer:
Outputs
Y0 = D.S1'.S0' S1 So Y0 Y1 Y2 Y3
Y1 = D.S1'.S0
0 0 D 0 0 0
Data D demux
0 1 0 D 0 0
Y2 = D.S1.S0' 1 0 0 0 D 0
Y3 = D.S1.S0
1 1 0 0 0 D
S1 S0
select
Demultiplexer
• The demultiplexer is actually identical to a decoder
with enable. A decoder with an enable input can
function as a demultiplexer (or demux)
Decoder + enable= demultiplexer
• The selection of a specific output line is controlled
by the bit values of ‘n’-selection lines.
Y0 = D.S1'.S0'
2x4
S1 Decoder Y1 = D.S1'.S0
data demux output S0 Y2 = D.S1.S0'
E Y3 = D.S1.S0
select
D
4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders with enables
13
4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders with enables
• When w=0, the top decoder is enabled and the other is
disabled. The bottom decoder outputs are all 0’s , and
the top eight outputs generate min-terms 0000 to 0111.
• When w=1, the enable conditions are reversed. The
bottom decoder outputs generate min-terms 1000 to
1111, while the outputs of the top decoder are all 0’s.
14
Implement the function
• F=∑(0,4,5)
F
F(a,b,c,d)=∑(0,1,3,5,12,13)
Implement the above boolean function using
a. 3:8 Decoder(s).
b. 2:4 Decoder(s).
16
F(a,b,c,d)=∑(0,1,3,5,12,13)
Implement the above boolean function using
a. 3:8 Decoder(s).
b. 2:4 Decoder(s).
You have to connect D0,D1,D3,D5,D12
& D13 with OR Gate
17
Note:
• Both mux and decoder can be used to design combinational circuit.
• Decoder are mostly used to decoding binary information and mux are
mostly used to select path between multiple sources and a single
destination.
