DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS- UE19EE203
Simplification of Boolean Expressions

SHANNON’S THEOREM

➢ Logic Minimization,Synthesis and Manipulation

➢ Two Types

1.Shannon’s Expansion Theorem(SET)

2.Shannon’s Reduction Theorem(SRT)

DIGITAL ELECTRONICS- UE19EE203

SHANNON’S THEOREM

Shannon’s Expansion Theorems(SETs)

➢ Shannon’s expansion assumes a switching algebra system.

➢ Available in two forms.

1. SOP (Sum-Of-Product)
2. POS(Product-Of-Sum)

➢ Both can be applied to any Logic function.

➢ Pick a variable , partition the switching function into two

cases: variable =1 and variable =0
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SHANNON’S THEOREM

❖ In SOP form– f(x,y,z,…)= xf(x=1,y,z,…) + x’f(x=0,y,z,…)

❖ In POS form – f(x,y,z,…)=[x+f(x=0,y,z….)] [x’+f(x=1,y,z….)]

❖ Also referred as ‘Expansion about a Variable’

Application: SET mainly used in Synthesis of Logic using

Multiplexers
DIGITAL ELECTRONICS- UE19EE203
SHANNON’S THEOREM

EXAMPLE: Consider a normal SOP Expression

f(w,x,y,z)=w’x’+(wx+y)z to expand by applying SET by isolating

variable ‘x’ both in SOP & POS form.

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SHANNON’S THEOREM
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SHANNON’S THEOREM

Shannon’s Reduction Theorems(SRTs)

➢ Available in Four Forms.

➢ Derived from SET.

➢ Can not apply to all expressions.

➢ Can be applied once function matches with the available

SRTs
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SHANNON’S THEOREM

❖ Theorem 1:xf(x,y,z,…….)=xf(x=1,y,z……..)

❖ Theorem 1:x’f(x,y,z,…….)=x’f(x=0,y,z……..)

❖ Theorem 1:x+f(x,y,z,…….)=x+f(x=0,y,z……..)

❖ Theorem 1:x’+f(x,y,z,…….)=x’+f(x=1,y,z……..)

NOTE: Application of Shannon’s Theorem not restricted to

particular number of variables and variable to isolate.
 DIGITAL ELECTRONICS- UE19EE203
SHANNON’S THEOREM

EXAMPLE: Consider a logic function f(w,x,y,z)=z’+z(wx’+y)+yz’+wxz to

reduce by using Shannon’s Reduction Theorems.

Solution: Since the given function resembles the SRT

x’+f(x,y,z,…….)=x’+f(x=1,y,z……..) ,need to apply the same as follows:

f(w,x,y,z)=z’+1(wx’+y)+y.1’+wx.1
=z’+wx’+y.0+wx
f =z’+wx’+wx
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Incomplete Boolean Functions & Don’t care Conditions

➢ Boolean Function?

➢ Complete Boolean function?

➢ Incomplete Boolean Function?

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Truth Tables to understand Different Boolean functions

Table 1 Table 2
x y z f x y z f
0 0 0 1 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 1 0 1 0 -
0 1 1 1 0 1 1 -
1 0 0 0 1 0 0 1
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
1 1 1 0 1 1 1 1

f(x,y,z)=∑m(0,2,3,6) f(x,y,z)=∑m(1,4,6,7)+
dc(2,3)
 DIGITAL ELECTRONICS- UE19EE203

Don’t Care Conditions

➢ There may be a combination of input values which

–will never occur
–if they do occur, the output is of no concern.
➢ The function value for such combinations is called a
don't care.
➢ They are denoted with x or –. Don’t cares can be used
to further simplify a function
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Summary of Incomplete Boolean Functions & Don’t care
Conditions

➢ Any Boolean Function where all input combination is

treated to get logic output is referred as Complete Boolean
function.

➢ Where some combinations are treated as not required is

referred as Incomplete Boolean function.

➢ Don’t care can be covered if it helps in Logic simplification

Otherwise leave it along.
 THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS- UE19EE203
Simplification of Boolean Expressions

Criteria for Minimality

➢ Cost

➢ Circuit Optimization

➢ Analysis
DIGITAL ELECTRONICS- UE19EE203

Prime Implicants/Prime Implicates

➢ Variable-Literal?

➢ Minterm-product term(Logical ANDing of Literal)

Ex:x’yz

➢ Implicant?
Ex:x’yz(If it implies the function)

➢ Prime Implicant?
Ex:f(x,y,z)=x’y+x’yz+xy
(x’yz is not Prime Implicant)
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Prime Implicants/Prime Implicates

➢ Maxterm-sum term(Logical ORing of Literal)

Ex:x’+y+z

➢ Implicate?
Ex:x’+y+z(If it implies the function)

➢ Prime Implicate?
Ex:f(x,y,z)=(x’+y)(x’+y+z)(x+y)
[(x’+y+z) is not a Prime Implicate]
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Irredundant Disjunctive/Conjunctive Expressions

➢ Irredundant Disjunctive Expressions:

SOP without Redundant term?

Ex:f(x,y,z)=x’y’+xyz+x’y’z+xz-----Redundant Disjunctive with

x’y’z & xyz as redundant terms

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Irredundant Disjunctive/Conjunctive Expressions

➢ Irredundant Conjunctive Expressions:

POS without Redundant term?

Ex:f(x,y,z)=(x’+y’)(x+y+z)(x’+y’+z)(x+z)-----Redundant

Conjunctive with (x’+y’+z) & (x+y+z) as redundant Terms.

DIGITAL ELECTRONICS- UE19EE203
Methods to Reduce(simplify) the Boolean Function

➢ Boolean Algebra

➢ Karnaugh Maps(K-Maps)

➢ Quine-McClusky Technique(Algorithm)

➢ Map Entered Variable(MEV)or Variable Entered

Map(VEM)or Compressed K-Map Technique
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Karnaugh Map Technique

➢ Better & More Elegant way

➢ Graphical Representation of Boolean function

➢ Diagram made up of Squares or cells

➢ Number of cells ?
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Karnaugh Map Technique

Steps to solve expression using K-map with Example.

Example 1.Z= ∑A,B,C(1,3,6,7)

Step 1: Select K-map according to the number of variables.

3-Varible map with 8 cells

4-Varible map with 16 cells

DIGITAL ELECTRONICS- UE19EE203
Karnaugh Map Technique

5-Varible map with 32 cells

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Karnaugh Map Technique

Step 2: Identify minterms or maxterms as given in problem.

For SOP put 1’s in blocks of K-map respective to the
minterms (0’s elsewhere).
For POS put 0’s in blocks of K-map respective to the
maxterms(1’s elsewhere).
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Karnaugh Map Technique

Step 3:Make rectangular groups containing total terms in power

of two like 2,4,8 ..(except 1) and try to cover as many elements
as you can in one group.

From red group we get product term—A’C

From green group we get product term—AB
Blue group indicates it is redundant-BC

Summing these product terms we get-

Final expression (A’C+AB)
DIGITAL ELECTRONICS- UE19EE203

Karnaugh Map Technique

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS- UE19EE203
K-MAPS

Example 2.For 4-Variable Expression

F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)
DIGITAL ELECTRONICS- UE19EE203

K-Maps

❖From red group we get product term—QS

❖From green group we get product term—Q’S’

❖Summing these product terms we get- Final expression

F=(QS+Q’S’)
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K-Map Simplication of POS Expressions

Example 1: For 3-Variable POS Expression

F(A,B,C)=π(0,3,6,7)
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K-Map Simplication of POS Expressions

From red group we find terms A B

Taking complement of these two A’ B’
Now sum up them (A’ + B’ )------Prime Implicate (i)

From brown group we find terms A’ B’ C’

Taking complement of these two A B C
Now sum up them (A + B + C)--------Prime Implicate(iii)

We will take product of these three terms :

Final expression (A’ + B’ ) (B’ + C’) (A + B + C)
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K-Map Simplication of POS Expressions
Example 2: For 4-Variable POS Expression

F(A,B,C,D)=π(3,5,7,8,10,11,12,13)
(C+D’+B’)-----------Prime Implicate (i)
(C’+D’+A)----------- Prime Implicate (ii)
(A’+C+D) )---------- Prime Implicate (iii)
(A’+B+C’) )---------- Prime Implicate (iv)

Finally we express these as product –

(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)
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K-Map Simplication for Statement Problem

Example1:Design a full adder by obtaining the

simplified expressions for the sum and carry outputs in POS form.
Inputs Decimal Outputs
Number of input variables = 3
A B Ci Equivalent S Co
Number of output variables = 2
0 0 0 0 0 0

0 0 1 1 1 0

0 1 0 2 1 0
Maxterm expansion for S = ∏M (0,3,5,6)
0 1 1 3 0 1

1 0 0 4 1 0
Maxterm expansion for Co = ∏M (0,1,2,4)
1 0 1 5 0 1

1 1 0 6 0 1

1 1 1 7 1 1
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Karnaugh Map Technique

Number of K-maps required = 2

S = (A + B + C ) (A + B̅ + C̅ ) (A̅ + B + C̅ ) (A̅ + B̅ + C )
i i i i

C = (A + B) (A + C ) (B + C )
o i i

ASSIGNMENT: Design a full adder by obtaining the

simplified expressions for the sum and carry outputs in POS
form.
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Karnaugh Map Technique for 5-Variables

Simplify the Boolean expression f (A,B,C,D,E) =

∑m (0,3,4,7,8,12,14,16,19,20,23,24,26,28)

The minimal SOP Expression is

f (A,B,C,D,E) = D̅E̅ + B̅DE + A̅BCDE̅ + ABC̅DE̅
 THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS- UE19EE203
K-Map Simplication of Incomplete Boolean Function

Minimize the following Incomplete Boolean function in SOP minimal

form using K-Maps.
F(A, B, C, D) = ∑m(1, 2, 6, 7, 8, 13, 14, 15) + dc(3, 5, 12)

NOTE: 1. To make group of cells,

we can use the "don't care" cells as
either 0 or 1.
2.We can also ignore that cell. We
mainly use the "don't care" cell to
make a large group of cells.

F = AC'D' + A'D + A'C + AB

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Karnaugh Map Technique

Advantages of K-Maps
1. The K-map simplification technique is simpler and less
error-prone compared to the method of solving the logical
expressions using Boolean laws.
2. It prevents the need to remember each and every Boolean
algebraic theorem.
3. It involves fewer steps than the algebraic minimization
technique to arrive at a simplified expression.
4. K-map simplification technique always results in minimum
expression if carried out properly.
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Karnaugh Map Technique

Disadvantages of K-Maps
1. As the number of variables in the logical expression
increases, the K-map simplification process becomes
complicated.

2. The minimum logical expression arrived at by using the K-

map simplification procedure may or may not be unique
depending on the choices made while forming the groups.
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Karnaugh Map Technique

Example to experience the Advantage of Simplification through K-

Maps compare to Boolean postulates, laws and theorems

Use a Karnaugh map to generate a simple Boolean expression

for this truth table, and draw a gate circuit equivalent to that
expression.

Challenge question: use Boolean algebra techniques to simplify

the table’s raw SOP expression into minimal form without the use
of a Karnaugh map.
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K-Map Technique
A B C D F
0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0
0 1 0 0 0

0 1 0 1 0
0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 0

1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
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K-Map Technique

CD
AB C’D’ C’D CD CD’
A’B’ 0 0 0 0

A’B 0 0 0 0

AB 0 0 1 1 AC

AB’ 1 0 1 1

The simplified logic is F=AC+AB’D’

AB’D’
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Karnaugh Map Technique

The gate circuit equivalent is as follows:

F=AC+AB’D’
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Karnaugh Map Technique

Now let us see the simplification through simple Boolean Algebra:

The Equation in Canonical SOP is

f=ABCD+ABCD’+AB’C’D’+AB’CD+AB’CD’

Step 1:ABC(D+D’)+AB’D’(C+C’)+AB’CD
since a+a’=1
The equation reduces to ABC+AB’D’+AB’CD
Step 2:F=ABC+AB’(CD+D’)
As per Distributive Law CD+D’ can be reduced to C+D’
Then equation further reduced to ABC+AB’C+AB’D’
Step 3:F=AC(B+B’)+AB’D’

Therefore the simplified expression is F=AC+AB’D’

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Karnaugh Map Technique

Example to experience the Disadvantage of Simplification through K-

Maps when number of variables are more.

Simplify the following 6-Variable Boolean function using K-Maps

F (A,B,C,D,E,F) = ∑ ( m0, m2, m8, m9, m10, m12, m13, m16, m18,
m24, m25, m26, m29, m31, m32, m34, m35, m39, m40, m42, m43, m47,
m48, m50, m56, m58, m61, m63 )

Since it is a 6-Variable expression we need K-Map with 64-cells

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Karnaugh Map Technique

COURTESY:
https://www.electricaltechnology.org/
DIGITAL ELECTRONICS- UE19EE203
Karnaugh Map Technique

The Simplified expression is F = D̅F̅ + A̅CE̅F + A̅B̅CE̅ + BCDF + AB̅EF

NOTE: Once the number of variables are more, the K-map

Technique is more tedious.
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS- UE19EE203
Simplification of Boolean Expressions

Inroduction to Quine-Mc Clusky Method

➢ K-map method, which is a convenient method for

minimizing Boolean functions up to 5 variables.

➢ Quine-McClusky technique which is computer Algorithm is

useful to get the prime implicants by repeatedly using the

following Boolean identity.

xy+xy’=x
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Quine-Mc Clusky Method to list Prime Implicants

Procedure of Quine-McCluskey Tabular Method

➢ Example 1:List all the prime implicants for the following

Canonical SOP Expression using Quine-McClusky tabular
method.
f(W,X,Y,Z)=∑m(2,6,8,9,10,11,14,15)

STEP1: Arrange the given min terms in an ascending order and

make the groups based on the number of ones present in their
binary representations.
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Quine-Mc Clusky Method to list Prime Implicants

Minterm Binary No.of

Equivalent I’s
2 0010 1 Index 1
6 0110 2 Index 2
8 1000 1 Index 1
9 1001 2 Index 2
10 1010 2 Index 2
11 1011 3 Index 3
14 1110 3 Index 3
15 1111 4 Index 4

NOTE: Index Indicates number of 1’s in the Binary number

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Quine-Mc Clusky Method to list Prime Implicants

Order Minterm Check Step 2 − Compare the min terms

in Binary mark/
Merge tick present in successive groups. If
INDEX 1 0010 √ there is a change in only one-bit
1000 √ position, then take the pair of those
INDEX 2 0110 √ two min terms. Place this symbol ‘_’
1001 √ in the differed bit position and keep
1010 √
the remaining bits as it is.
INDEX 3 1011 √
1110 √
INDEX 4 1111 √

All minterms covered in pairs

indicated by check mark ‘√’
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Quine-Mc Clusky Method to list Prime Implicants

Combined Pair in Check

minterm/Mer Binary mark/
ged minterm Merge tick
Step 3 − Repeat step 2 with newly formed
(2,6) 0–10 √ terms till we get all prime implicants.
(2,10) – 010 √
(8,9) 100– √
(8,10) 10– 0 √
(6,14) – 110 √
(9,11) 10– 1 √
(10,11) 101– √
(10,14) 1– 10 √
(11,15) 1– 1 1 √
(14,15) 111– √
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Quine-Mc Clusky Method to list Prime Implicants

Combined Quad in Check

Pairs Binary mark/
Merge tick
(2,6, 10,14) ––10 yz’(Prime Implicant 1)

(8,9,10,11) 10– – wx’Prime Implicant 2)

(10,11,14,15) 1–1– wy Prime Implicant 3)

No further combination

Therefore the resultant Prime Implicants are 3

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Quine-Mc Clusky Method

➢ Example 2:f(a,b,c,d)=∑m(0,1,2,5,6,7,8,9,10,14)
List all possible prime implicants for the above Boolean
function using Quine-McClusky Method.

Step 1:
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Quine-Mc Clusky Method

Step 2 Step 3 Step 4

PI 4
PI 5

PI 1
PI 6

PI 2
PI 3
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Quine-Mc Clusky Method

The Prime Implicants are PI 1 -----(1,5) 0–01 a’c’d

PI 2 -----(5,7) 01–1 a’bd

PI 3------(6,7) 011– a’bc

PI 4-----(0,1,8,9) –00– b’c’

PI 5-----(0,2,8,10) – 0 – 0 b’c’

PI 6-----(2,6,10,14) --10 cd’

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Quine-Mc Clusky Method

Important :

➢ In order to accurately use the Quine-McCluskey, the

function needs to be given as a sum of minterms .

➢ To find all prime implicants, all possible pairs of minterms

should be compared and combined whenever possible.

➢ Once expression is with Maxterms, proceed with minterms

and finally take the complementation of Prime Implicant to
know the Prime Implicate since MAXTERM=minterm’
(Mi=mi’)
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Quine-Mc Clusky Method to find Prime Implicates

List all the Prime Implicates of the given Boolean function using
Quine-McCluskey Technique.
f (a,b,c,d)=∏M(0,1,2,3,5,7,8,10,14,15)

➢ Need to treat all Maxterms or Implicates as minterms.

f’ (a,b,c,d)=∑m(0,1,2,3,5,7,8,10,14,15)

➢ Follow steps to list Prime Implicants.

➢ Finally need to take complementation to get Prime

Implicates.
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Quine-Mc Clusky Method to find Prime Implicates

❖ Done with listing of

minterms/implicants
as per index
❖ Minterm ‘0’ not
included in the table
and 0 is adjacent to
all index 1 group
minterms
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Quine-Mc Clusky Method to find Prime Implicates

❖ Minterm ‘0’ not

√
√ included in the table
√ and 0 is adjacent to
√ all index 1 group
√
minterms
√
❖ Done with
√ comparison of
√ minterms/implicants
in successive groups
√ to form pairs
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Quine-Mc Clusky Method to find Prime Implicates

√ √
√ √
√ √

√ √
√ √
√ √
√
√
√
√ √
√
√

√
DIGITAL ELECTRONICS
Quine-Mc Clusky Method to find Prime Implicates

❖No further comparison .

❖Resultant list of Prime Implicants are as follows:

Prime Implicates are:
1. (0,1,2,3) 0 0 – – a’b’
1.(a+b)
2. (0,8,2,10) – 0 – 0 b’d’
2. (b+d)
3. (1,3,5,7) 0––1 a’d 3.(a+d’)
4. (7,15) –111 bcd 4.(b’+c’+d’)
5. (14,15) 111– abc 5. (a’+b’+c’)
 DIGITAL ELECTRONICS
Quine-Mc Clusky Method for Incomplete Boolean Function

Example 1: f(W, X,Y,Z) =∑m(0,3,5,6,7,10,12,13)+dc(2,9,15)

➢ Significance of Don’t care terms

➢ Treat Don’t care terms as Minterms in SOP

expression/Maxterms in POS Expression

➢ Merge dc terms with regular minterms in the equation with *

as follows:

f(W, X,Y,Z) =∑m(0,2*,3,5,6,7,9*,10,12,13,15*)

➢ Follow the steps as similar to previous examples.

DIGITAL ELECTRONICS-
Quine-Mc Clusky Method for Incomplete Boolean Function

Step 1 : Divide all the minterms (and don’t cares) of a function

into groups as per Index(no. of 1’s)
Step 2: Merge minterms from adjacent groups to form a new
implicant table

√
√
√
√
√
√
√
√
√
√
√
DIGITAL ELECTRONICS-
Quine-Mc Clusky Method for Incomplete Boolean function

Step 3: Repeating Step 2 to

PI 1 combine Pairs to form quad
√
√
PI 2 PI 5
√
√ PI 6
√
√
PI 3
PI 4
√
No more merging possible!So
√
that there exists 6 PIs
DIGITAL ELECTRONICS
Quine-Mc Clusky Method for Incomplete Boolean function

The Prime Implicants are:

❖ PI 1:(0,2) : 0 0 d 0-----w’y’z’
❖ PI 2:(2,10) :d 0 1 0------x’yz’

❖ PI 3:(9,13) :1 d 0 1-----wy’z

❖ PI 4:(12,13) :1 1 0 d-----wxy’

❖ PI 5:(2,3,6,7) :0 d 1 d-----w’y

❖ PI 6:(5,7,13,15) :d 1 d 1-----xz
DIGITAL ELECTRONICS
Quine-Mc Clusky Method

IMPORTANT:

➢ Quine–McCluskey method is a tabular method

➢ Has an advantage over Karnaugh maps when a large number

of inputs are present.

➢ Method does not require pattern recognition.

➢ Can be programmed and implemented in a computer

DIGITAL ELECTRONICS
Quine-Mc Clusky Method

QUIZ QUESTIONS:

1. Quine-McCluskey technique is cellular method of finding

Prime Implicants.
a) TRUE b) FALSE

2. In QM Technique,the following process is not required.

a) Arranging minterms as per number 1’s

b) Pattern Recognition
c) Comparing & combining successive group minterms
d) Putting DASH symbol in the bit difference place.
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Decimal Quine-Mc Clusky Method

❖ Computational complexity still remains high.

❖ Due to expressing each minterm in 1 0 –Notation.

❖ Proceed with Decimal Numbers.

❖ Resulatant method termed as ‘Decimal Q M Technique’.

DIGITAL ELECTRONICS

Decimal Quine-Mc Clusky Method to find Prime Implicants/Implicates

Example 1: f(W,X,Y,Z) = ∑m(5,7,9,11,13,15).Find all the Prime

Implicants using Decimal Q M Technique.

Step 1:Arrange the minterms as per the index in decimal form.

INDEX MINTERM CHECK Step 2:Condition to be satisfied to
MARK combine minterms to form pair group:
0 NIL The difference between
1 NIL minterms(Higher group-Smaller group)
2 5 √ should be power of two
9 √ P

3 7 √
11 √ Q
13 √
4 15 √ R
DIGITAL ELECTRONICS
Decimal Quine-Mc Clusky Method to find Prime Implicants/Implicates

Compared Groups Newly Check

formed mark
Group
P & Q(Q-P) 5,7(2) √
5,13(8) √ x
9,11(2) √
9,13(4) √
Q & R(R-Q) 7,15(8) √
11,15(4) √ y
13,15(2) √

Step 3:Conditions to be satisfied to combine

minterms to form pair group:
1. The difference inside parenthesis should be same.
2. To combine the difference between both set of
numbers should be same and power of 2.
DIGITAL ELECTRONICS
Decimal Quine-Mc Clusky Method to find Prime Implicants/Implicates

Combined Groups Newly formed Groups

x & y (y-x) 5,7,13,15(2,8) PI 1
9,13,11,15(4,2) PI 2

No further steps possible to combine any quad

DIGITAL ELECTRONICS
Decimal Quine-Mc Clusky Method to find Prime Implicants/Implicates

Step 4:Converting Decimal form of Prime implicants to Algebraic form .

➢ Based on position weightage of Boolean Variable in 8 4 2 1 code

basis place parenthesis difference under that particular position as
‘-’(dash)

➢ Smallest minterm in the group should be represented as 1 and rest

all positions with 0
DIGITAL ELECTRONICS

Decimal Quine-Mc Clusky Method to find Prime Implicants/Implicates

Variables defining the function are w x y z

Position weights of these variables 8 4 2 1

PI 1: 5,7,13,15(2,8) - 1 - 1 xz

PI 2: 9,13,11,15(4,2) 1 - - 1 wz

So that the resusltant Prime Implicants are xz & wz

DIGITAL ELECTRONICS
Decimal Q M Method for Incomplete Boolean Function

Example 2: Find all the Prime Implicants of the Boolean function

f(a,b,c,d) =∑m(0,3,5,6,7,10,12,13)+dc(2,9,15) using Decimal Q M
Technique.
STEP 1
INDEX MINTERM CHECK
MARK
0 0 √ P

1 2* √ Q

2 3 √
5 √
6 √ R
9* √
10 V
12 √
3 7 √ S
13 √
4 15* √ T
DIGITAL ELECTRONICS
Decimal Q M Method for Incomplete Boolean Function
STEP 2
Compared Groups Newly Check No combination of w & x since no
formed mark same difference in parenthesis
Group

P & Q(Q-P) 0.2*(2) PI 1 w

Q & R(R-Q) 2*,3(1) √
2*,6(4) √ x
2*,10(8) PI 2
R & S(S-R) 3,7(4) √
5,7(2) √
5,13(8) √ y
6,7(1) PI 3
9*,13(4) √
12,13(1) PI 4
S & T(T-S) 7,15*(8) √
z
13,15*(2) √
DIGITAL ELECTRONICS
Decimal Q M Method for Incomplete Boolean Function
STEP 3

Combined Groups Newly formed Check

Groups mark
w & x (x-w) NIL
x & y (y-x) 2*,3,6,7(1,4) PI 5

y & z (z-y) 5,13,7,15*(8,2) PI 6

No further steps possible to combine any quad!

DIGITAL ELECTRONICS
Quine-Mc Clusky Method

Variables defining the function are a b c d

Position weights of these variables 8 4 2 1

PI 1: 0.2*(2) 0 0 - 0 a’b’d’

PI 2: 2*,10(8) - 0 1 0 b’cd’

PI 3: 6,7(1) 0 1 1 - a’bc

PI 4: 12,13(1) 1 1 0 - abc’
DIGITAL ELECTRONICS
Quine-Mc Clusky Method

Variables defining the function are a b c d

Position weights of these variables 8 4 2 1

PI 5: 2*,3,6,7(1,4) 0 - 1 - a’c

PI 6: 5,13,7,15*(8,2) - 1 - 1 bd

So that the resultant Pis are a’c,bd,a’b’d’,b’c’d’,a’bc,abc’

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Simplification after QM method

➢ Methods available for further simplification.

1. PI Table reduction Technique

• Can find one possible minimal expression/minimal cover

2. PETRICK’S Method

• Can find all possible minimized expressions

 DIGITAL ELECTRONICS

Prime Implicant/Implicate table Reduction Technique

Procedure for Table Reduction Technique:

Step 1. Construct Prime Implicants Table(Raw PI Table)

Step 2. Find Primary Essential Prime Implicants & score out

that row.

Step 3. If any rows & columns left construct table with those
Pis which is referred as Cyclic table.
DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Step 4. Apply either Column Reduction Technique first or Rows

Reduction technique.

Step 5. If all rows & columns covered under this technique ,write
minimal expression with all Primary and secondary Pis.
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Let us consider an example to apply table reduction technique .

Example 1:Find the Minimal Sum expression for the following
Boolean function using QM Technique followed by Table Reduction
Technique.
f(a,b,c.d) = Σm(0,1,2,5,6,7,8,9,10,14)
The PIs are
1. (0,1,8,9) – 0 0 – b’c’
2. (0,2,8,10) – 0 – 0 b’d’
3. (2,6,10,14) – – 1 0 cd’
4. (1,5) 0 – 0 1 a’c’d
5. (5,7) 0 1 – 1 a’bd
6. (6,7) 0 1 1 – a’bc
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique
Step 1. Construct Prime Implicants Table(Raw PI Table)
Minterms m0 m1 m2 m5 m6 m7 m8 m9 m10 m14
PIs
b’c’ x x x x

b’d’ x x x x

cd’ x x x x

a’c’d x x

a’bd x x

a’bc x x
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Step 2. Find Primary Essential Prime Implicants & score out

that row.
❖ Any single ‘x’ under the column should be encircled.

❖ That corresponding row can be treated as essential row/PI.

❖ The minterms which that row covering can be removed by

drawing a line on that.
DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Minterms m0 m1 m2 m5 m6 m7 m8 m9 m10 m14

PIs
b’c’ x x x x EPI 1

b’d’ x x x x

cd’ x x x x EPI 2

a’c’d x x

a’bd x x

a’bc x x
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Step 3. If any rows & columns left construct table with those
PIs which is referred as Cyclic table.

Minterms m5 m7
PIs

b’d’

a’c’d x

a’bd x x

a’bc x
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Procedure to apply in Column Reduction Technique:

❖ Identify two Equal Columns.

❖ Check for Dominance between those two based on number

of ‘x’ it contains.

❖ Eliminate Dominating column and retain dominated column

❖ If dominance is not there Eliminate one and retain one

❖ Retained Column should not be eliminated further.

 DIGITAL ELECTRONICS

Prime Implicant/Implicate table Reduction Technique

Procedure to apply Row Reduction Technique:

❖ Identify two Equal Rows.

❖ Check for Dominance between those two based on number

of ‘x’ it contains.

❖ Add extra column to as cost column.

❖ Cost of a row is Number of literals of that prime implicant+1

DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

❖ Eliminate Dominated row with equal or more cost.

❖ If dominance is not there Eliminate one(with high cost/equal)

and retain one

❖ Retained Row should not be eliminated further.

 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Minterms m5 m7 Cost Here in this table,row a’bd

PIs
dominating both rows a’c’d & a’bc, so
b’d’ 3 that dominated rows can be
eliminated & Columns m5 & m7 are
a’c’d x 4 equal ,no dominance retain one &
eliminate one.
a’bd x x 4
EPI 3

a’bc x 4

So that the minimal sum is f=b’c’+cd’+a’bd

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique for
Incomplete Boolean function

Example 1: f(W, X,Y,Z) =∑m(0,3,5,6,7,10,12,13)+dc(2,9,15)

The Prime implicants are:
❖ PI 1:(0,2*) : 0 0 d 0-----w’x’z’
❖ PI 2:(2*,10) :d 0 1 0------x’yz’

❖ PI 3:(9*,13) :1 d 0 1-----wy’z

❖ PI 4:(12,13) :1 1 0 d-----wxy’

❖ PI 5:(2*,3,6,7) :0 d 1 d-----w’y

❖ PI 6:(5,7,13,15*) :d 1 d 1-----xz
 DIGITAL ELECTRONICS

Prime Implicant/Implicate table Reduction Technique

❖ Need not treat Don’t care terms in the PI Table
Minterms m0 m3 m5 m6 m7 m10 m12 m13
PIs
w’x’z’ x

x’yz’ x

wy’z x

wxy’ x x

w’y x x x

xz x x x
DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique
STEP 2: Finding Primary Essential Prime Implicants
Minterms m0 m3 m5 m6 m7 m10 m12 m13
PIs
w’x’z’ x EPI 1

x’yz’ x EPI 2

wy’z x

wxy’ x x EPI 3

w’y x x x EPI 4

xz x x x EPI 5
DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

• Out of 6 Prime Implicants 5 are essential to write the minimal

expression. In this case column & row reduction technique is
not required.

• The minimal sum is f= w’x’z’ +x’yz’+wxy’+w’y+xz

DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

Verification with Karnaugh maps method:

f(W, X,Y,Z) =∑m(0,3,5,6,7,10,12,13)+dc(2,9,15)

❖ Given expression is 4-variable incomplete Boolean function.

❖ Need to use 16 cells map.

❖ Treat don’t care terms as minterms(as 1) since it is SOP

DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

w’x’z’
yz
wx y’z’ y’z yz yz’
1 0 1 x
w’x’
0 1 1 1 w’y
w’x
1 1 x 0 xz
wx
wx’ 0 x 0 1

wxy’ x’yz’

The minimal sum is f= w’x’z’ +x’yz’+wxy’+w’y+xz

Verified and found correct
 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

IMPORTANT TO REMEMBER :
❖ PI Table reduction is split in to
1. Column Reduction
2. Row Reduction

❖ Column Reduction
Need to check equality & Dominance

Can delete Dominating Column if dominance occurs

Otherwise can retain one & delete one

Retained column can never be eliminated

DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique

❖ Row Reduction
Need to check equality & Dominance

Can delete Dominated row if dominance occurs & also check cost
of the prime implicant.

Dominated row with equal or more cost can be eliminated

Otherwise can retain one & delete one

Retained row can never be eliminated

 DIGITAL ELECTRONICS
Prime Implicant/Implicate table Reduction Technique
Random Example to illustrate the complete Procedure of Table
Reduction Technique.
Minterms C1 C2 C3 C4 C5 C6 C7

PIs
r1 x x x

r2 x x

r3 x x x x

r4 x x x

r5 x x

r6 x x
DIGITAL ELECTRONICS

Prime Implicant/Implicate table Reduction Technique

Minterms C1 C2 C3 C4 C5 C6 C7 COST

PIs
r1 x x x 3

r2 x x 4

r3 x x x x 3

r4 x x x 3

r5 x x 5

r6 x x 4
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Petrick’s Method for simplification

A more systematic way to find all minimum solutions from a

prime implicant chart for both SOP & POS after listing PIs using
QM Technique.

Steps to follow in PETRICK’s Method are;

1. Construct PI Table.

2. No need of finding Primary Essential Pis in this method.

3. Represent each Prime Implicant by an alphabet.

4. Write P-Equation/Product Equation/Petrick’s Equation.

 DIGITAL ELECTRONICS

Petrick’s Method for simplification

5. Simplify the equation using basic Boolean Rules.

6. Each term Present in the simplified equation is one possible

Minimal Expression.

7.Can choose best among many for implementation based on

Cost Criteria.
DIGITAL ELECTRONICS
Petrick’s Method for simplification

Example:Find all possible minimal sum expression for the

following Boolean Function using Decimal QM Technique and
Petrick’s Method .Choose best for implementation and justify
your answer.
f(a,b,c,)= ∑m(0,1,2,5,6,7)
Ind Minter Check Group of Pairs Check Mark
ex ms Mark pairs
0 0 √ 1 0,1(1) No further
1 1 √ 0,2(2) combination
2 √ 2 1,5(4)
2 5 √ 2,6(4)
6 √ 3 5,7(2)
3 7 √ 6,7(1)
DIGITAL ELECTRONICS
Petrick’s Method for simplification

Group of Pairs Check NO FURTHER COMBINATION

pairs Mark OF PAIRS TO FORM QUADS!

1 0,1(1) PI 1 Total Prime Implicants 6

0,2(2) PI 2 Algebraic form of Pis:
a b c
2 1,5(4) PI 3
4 2 1
2,6(4) PI 4
PI 1: 0 0 - :a’b’
3 5,7(2) PI 5 PI 2: 0 - 0 :a’c’
6,7(1) PI 6 PI 3: - 0 1 :b’c
PI 4: - 1 0 :bc’
PI 5: 1 - 1 :ac
PI 6: 1 1 - :ab
DIGITAL ELECTRONICS
Petrick’s Method for simplification
Construct PI Table as below:
Minterm m0 m1 m2 m5 m6 m7
PIs
a’b’ x x
A

a’c’ x x
B

b’c x x
C

bc’ x x
D

ac x x
E

ab x x
F
 DIGITAL ELECTRONICS
Petrick’s Method for simplification

Write P-Expression as follows:

P=(m0) (m1) (m2) (m5) (m6) (m7)

=(A+B) (A+C) (B+D) (C+E) (D+F) (E+F)

[Simplify using basic Boolean algebra]

The simplified P-Equation consisting of 5 terms & each

represents one minimal expression.

P=ABEF+ADCF+BCDE+ADE+BCF
DIGITAL ELECTRONICS
Petrick’s Method for simplification

1. f1=ABEF=a’b’+a’c’+ac+ab=12

2. f2=ADCF=a’b’+bc’+b’c+ab-12

3. f3=BCDE=a’c’+b’c+bc’+ac=12

4. f4=ADE=a’b’+bc’+ac=9

5. f5 =BCF=a’c’+b’c+ab=9

Based on cost criteria, expression 4 or 5 is suitable for

implementation since both having less cost compare to others.
 DIGITAL ELECTRONICS
Petrick’s Method for simplification

Example for Simplification of Incomplete Boolean function

using Petrick’s Method .
F(a,b,c,d)=∏M(0,6,7,8,9,13)+dc(5,15)

With the help of Quine-McCluskey Technique,we can list

Prime implicants as follows:
1. b’c’d’(0,8)
2. ab’c’(8,9)
3. a’bc (6,7)
4. ac’d (9,13)
5. bd (5*,7,13,15*)

Proceed to construct PI Table to apply Petrick’s Method

DIGITAL ELECTRONICS
Petrick’s Method for simplification

Minterm m0 m6 m7 m8 m9 m13
PIs
b’c’d’ x x
A

ab’c’ x x
B

a’bc x x
C
ac’d x x
D
bd x x
E
DIGITAL ELECTRONICS

Petrick’s Method for simplification

P-Expression can be written as follows:

P=m0.m6.m7.m8.m9.m13

=(A)(C)(C+E)(A+B)(B+D)(D+E)
=(AC+AE+AB+AD+B+BD)(D+E)
=(AC+AE+AD+B)(D+E)
=ACD+ACE+ADE+AE+AD+ADE+BD+BE
P=AE+AD+BD+BE

The P-Expression consisting of 4 Terms in turn the minimized

expressions are 4.
DIGITAL ELECTRONICS
Petrick’s Method for simplification

P=AE+AD+BD+BE

f1=AE=b’c’d’+bd=7

f2 = AD=b’c’d’+ac’d=8

f3=BD=ab’c’+ac’d=8

f4=BE=ab’c’+bd=7

Best suitable for simplification is either f1 or f4 since cost is less.

NOTE:Student can verify with K-Map Technique!

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

❖Compressed K-Map Technique

❖One or more variable can be treated as Map entered Variable.

❖Can have reduced number of cells.

❖For example,if we wish to simplify 3-variable expression,we

need 8-cells.
DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

❖ This method allows the reduction of cells by treating one

variable as Map entered variable .

❖ So out of 3-variables one is directly go into the map and

other two are map variables which forms 4-cells map.

❖ 50% cell requirement reduced.

❖ This method also popularly known as Variable Entered

Map(VEM)Technique.
DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

Example 1:Simplify the following Boolean expression using MEV

Technique by treating LSB as Map Entered Variable.

F(a,b,c)=∑m(0,1,4,5,7)

Let us see the detailed Steps involved in this method.

❖ Construct MEV Table(Extension of Truth Table)

❖ Enter the cells of the Map from cell entry column of MEV
Table.
DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

❖ For Grouping of adjacent cells,need to follow the procedure as

below:

Step 1:Cover all MEVs as larger group as possible with the help of
1-cells & don’t care cells by treating MEV’s cells as 0-cells.

Step 2:Cover all MEV’s as larger group as possible with the help of
1-cells & don’t care cells by treating MEV cells as 0-cells.
 DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)
❖ Step 3:Cover all incompletely covered 1-cells.(the 1-cell not
covered in both steps 1 & 2 is referred as incompletely covered
1-cell)

❖ For each group write common Literals ANDing with MEV or

MEV’ if any internal to Group.

❖ By logically ORing all the terms ,we can arrive at simplified

Expression.
 DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

Map Map O/P Cell

Variables Entered Function Entry
Variable
a b c f
Cell 0 0 0 0 1 1
0 0 1 1
0 1 0 0 0
Cell 1
0 1 1 0
1 0 0 1
Cell 2 1 0 1 1 1
1 1 0 0
Cell 3 1 1 1 1 c
DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

4-Variable K-Map

b
a b’ b
a’ 1 0 Step 3 : b’

a
1 c Step 1 :ac

The simplified Expression is f=b’+ac

NOTE:Student can try to cross verify with normal K-Maps

 DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

Example 2:Simplify the following Boolean expression using MEV

Technique by treating w,x,y as Map Variables.

F(w,x,y,z)=∑m(2,3,4,5,10,12,13)

➢ Since w,x & y are Map variables,z is Map Entered Variable.

➢ The cell requirement reduced from 16 to 8.

➢ That’s why the name compressed K-Maps.

DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

Map Variables Map Entered O/P Cell Entry

Variable Function
w x y z f
Cell 0 0 0 0 0 0 0
0 0 0 1 0
0 0 1 0 1 1
Cell 1
0 0 1 1 1
0 1 0 0 1 1
Cell 2
0 1 0 1 1
0 1 1 0 0 0
Cell 3
0 1 1 1 0
1 0 0 0 0 0
Cell 4
1 0 0 1 0
Cell 5 1 0 1 0 1 Z’
1 0 1 1 0
1 1 0 0 1 1
Cell 6
1 1 0 1 1
1 1 1 0 0 0
Cell 7 1 1 1 1 0
DIGITAL ELECTRONICS
Map Entered Variable Technique(MEV Technique)

w’x’y
xy
w x’y’ x’y xy xy’
w’ 0 1 0 1 xy’
w 0 z’ 0 1

x’yz’

The Minimal Expression is f=x’yz’+w’x’y+xy’

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
UE19EE203
Simplification of Boolean Expressions

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL UE19EE203
MEV/VEM TECHNIQUE

MEV for Incomplete Boolean function

❖ Example 1:Find the minimal sum for the following Incomplete
Boolean function using MEV technique by treating LSB as MEV

f(a,b,c,d)=∑m(0,2,3,4,5,13,15)+dc(8,9,10,11)
DIGITAL ELECTRONICS- UE19EE203

MEV/VEM TECHNIQUE

Map Variables Map Entered Function Cell Entry

Variable
a b c d f
Cell 0 0 0 0 0 1 d’
0 0 0 1 0
0 0 1 0 1 1
Cell 1 0 0 1 1 1
0 1 0 0 1 1
Cell 2 0 1 0 1 1
0 1 1 0 0 0
Cell 3
0 1 1 1 0
1 0 0 0 x
Cell 4 1 0 0 1 x X
1 0 1 0 x
Cell 5 1 0 1 1 X X
1 1 0 0 0
Cell 6 1 1 0 1 1 d
1 1 1 0 0
Cell 7 1 1 1 1 1 d
DIGITAL ELECTRONICS- UE19EE203
MEV/VEM TECHNIQUE

bc
a b'c’ b’c bc bc’

a’ d’ 1 0 1 a’bc’

a x x d d

b’d’ b’c ad

The minimal Sum is f=a’bc’+ad+b’c+b’d’

DIGITAL ELECTRONICS- UE19EE203
MEV/VEM TECHNIQUE

MEV for POS Boolean Function

❖ Example 1: Find the minimal product expression for the

following Incomplete Boolean function using VEM technique
by treating LSB as MEV

F(a,b,c,d)=∏M(1,2,5,7,9,10,13,14)+dc(8,12,15)
DIGITAL ELECTRONICS- UE19EE203
MEV/VEM TECHNIQUE

Map Variables Map Entered Function Cell Entry

Variable
a b c d f
0 0 0 0 1 d’
Cell 0 0 0 0 1 0
0 0 1 0 0 d
Cell 1 0 0 1 1 1
0 1 0 0 1 d’
Cell 2 0 1 0 1 0
0 1 1 0 1 d’
Cell 3 0 1 1 1 0
1 0 0 0 X 0 or d’
Cell 4
1 0 0 1 0
1 0 1 0 0 d
Cell 5
1 0 1 1 1
1 1 0 0 X 0 or d’
Cell 6 1 1 0 1 0
1 1 1 0 0
1 1 1 1 x 0 or d
Cell 7
DIGITAL ELECTRONICS- UE19EE203

MEV/VEM TECHNIQUE

MEV F CELL MEV F CELL MEV F CELL

ENTRY ENTRY ENTRY
0 0 0 1 0 0
1 0 0 1 1 1 1 1 MEV

MEV F CELL MEV F CELL MEV F CELL

ENTRY ENTRY ENTRY
0 1 0 X 0 or 0 0 0 or
MEV’ 1 0 MEV’ 1 X MEV
1 0
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MEV/VEM TECHNIQUE

MEV F CELL MEV F CELL

ENTRY ENTRY
0 X 1 0 1 1 or
1 1 orMEV 1 X MEV’

MEV F CELL
ENTRY
0 X
1 X X
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MEV/VEM TECHNIQUE

Steps to follow in grouping on the map in case of dual entries are:

1. In case of entries of MEV along with 1 or 0 ,the way we are treating

that particular dual entry cell in step 1 must be retained till the end
of grouping.

2. Need to do large groups

3. Need not repeat grouping of MEV or MEV’ cells which results in to

redundant groups.
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MEV/VEM TECHNIQUE

bc
a b'c’ b’c bc bc’

a’ d’ d d’ d’

a
0 or d’ d 0 or d 0 or d’

(b+c’+d) (b’+d’) (c+d’)

(a’+b’+c’)
The minimal Product is f=(b+c’+d) (a’+b’+c’) (b’+d’) (c+d’)
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MEV/VEM TECHNIQUE

Verification of answer with K-Maps

cd
ab c’d’ c’d cd cd’

a’b’ 1 0 1 0 (b+c’+d)

a’b
1 0 0 1 (b’+d’)
ab
x 0 x 0 (a’+b’+c’)
ab’ x 0 1 0
(c+d’)
The minimal Product is f=(b+c’+d) (a’+b’+c’) (b’+d’) (c+d’)
 DIGITAL ELECTRONICS- UE19EE203
Summary of Unit 1

❖ Simplification results in to less number of literals which inturn

reduce the Hardware requirement in Digital Logic.

❖ Boolean postulates, laws and theorems are bit tedious to use

when expression is complex.

❖ Karnaugh maps are cellular method for simplification but at the

level of increased number of variables(beyond 5 or 6 variables)
method will be complex.

❖ Quine-McCluskey technique is one of the computer Algorithm to

list all possible Prime Implicants/Implicates.
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Summary of Unit 1

❖ PI Table reduction technique is one of the tool for further

simplification after Q M Technique to arrive at single minimal
expression.

❖ Petrick’s Method is another tool for the same but to arrive at all
possible minimal expressions.

❖ Map Entered Variable (MEV)/Variable Entered

Map(VEM)/Compressed K-Map is another efficient tool for
simplifying Boolean expressions.
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@pes.edu
+91 80 6666 3333 Extn 273