SCOE Vadgaon Pune
UNIT III
Algorithmic State Machine
Digital Electronics & Logic
ASM
Design
Syllabus
ASM & VHDL
• Algorithmic State Machines: Finite State Machines (FSM) and
ASM, ASM charts, notations, construction of ASM chart and
realization for sequential circuits, Examples: Sequence Generator,
Types of Counter.
• VHDL: Introduction to HDL, Data Objects & Data Types, Attributes.,
VHDL- Library, Design Entity, Architecture, Modeling Styles,
Concurrent and Sequential Statements,
• Design Examples: VHDL for Combinational Circuits-Adder, MUX,
VHDL for Sequential Circuits, Synchronous and Asynchronous
Counter.
Digital Electronics & Logic
ASM
Design
Books to Refer
Text Books:
• R.P. Jai , ― Moder Digital Electro ics , Tata
McGraw-Hill, 2012.
• Stephen Brown, Zvonko Vranesic, ―
Fu da e tals of Digital Logic with VHDL Desig ,
McGraw-Hill.
Reference Books:
A VHDL Primer, J. Bhaskar
Digital Electronics & Logic
ASM
Design
Introduction
ASM chart: It is similar to conventional flowchart but
interpreted in different manner.
It is a graphical view.
ASM chart is basically flowchart for hardware algorithm.
It considers timing relationships.
It is useful to design the hardware of a sequential circuits
as per the specifications.
It is suitable for describing the sequential operations of a
digital system.
Digital Electronics & Logic Design ASM
ASM Chart Notations
The state box The decision box The conditional box
It is used for indicating the It describes the effect of an Its rounded corners are
state of the controller in the input on the control. different from the state box
control sequence
It is rectangular in shape. It is diamond shaped box. It is oval shaped.
In this box, information will The input condition to be The input path to this box
be written as register tested will be written inside. must come from one of the
operations or output value exit paths of the decision
for given state. box.
For each state there is one It has two or more exit paths. These are familiar in
entry and exit point. conventional flowcharts.
Entry
State Name Binary code
Register operation or Condition Conditional outputs
Outputs Expression or actions
0(false) 1(true)
exit
Digital Electronics & Logic
ASM
Design
Example
entry
q1 001
1 0
D
q2 010 q3 100
Digital Electronics & Logic
ASM
Design
What is VHDL?
VHDL=V + HDL
V.H.S.I.C. means Very High Speed Integrated Circuit
V.H.D.L. = Very High Speed Integrated Circuit Hardware
Description Language.
A documentation language
A simulation language
A synthesis language
Technology independent logic design
Digital Electronics & Logic Design ASM
HDL is a technique for describing the hardware
associated with a digital system.
The VHDL design (also called a model) is similar
to the structure of an ordinary program, such as
a C program.
Digital Electronics & Logic Design ASM
C-Compiler
main( ) Processor
{
( Software )
( Hardware )
int x=10,y=20,z; The ALU Then
Syntax Check
z=x+y; Adds the 2 nos. 10 & 20 and
Generates .obj
printf ( “ %d “, z Generates the result 30.
File ie. Program
);
into machine
getch( ) ; language
} (11000011….)
On your PC
VHDL SYNTHESIS CPLD / FPGA
Program TOOL ( Programmable H/W )
( XILINX Software ) The above device then
operates as the desired
For Syntax Check Digital Circuit
Converts VHDL Programming
Half-Adder , MUX , Instructions
( Half-Adder , MUX ,
Counter , Code Program Counter ,
into a GATE-
µController LEVEL NETLIST Or even a MicroController
)
(11000011….) ASM
Digital Electronics & Logic Design
A VHDL Progra ay co sist of….
• ENTITY Declaration.
compulsory
• ARCHITECTURE Body.
• Configuration Declaration.
• Package optional
* Package Body.
* Package Declaration.
All Declarations are called P.D.U’s ( Primary
Design Units )
All
DesignBody’s are called S.D.U’s ( Secondary Design
Digital Electronics & Logic
ASM
Syntax For Entity Declaration
ENTITY entity_name IS
PORT
(
signalname_1 : [ MODE ] [ DATATYPE ] ;
signalname_2 : [ MODE ] [ DATATYPE ] ;
signalname_3 : [ MODE ] [ DATATYPE ] ;
. NO Semi-
. colon after
signalname_n : [ MODE ] [ DATATYPE ]
); Last Signal
END entity_name ;
IN / OUT / 1) BIT ( 2-Valued Logic )
INOUT 2) STD_LOGIC ( 9-Valued LOGIC ) --
Preferred
Digital Electronics & Logic
ASM
Design
Example of ED For an AND Gate
A
and_gate Y
B
ENTITY and_gate IS
PORT
(
A : IN STD_LOGIC ;
B : IN STD_LOGIC ;
Y : OUT STD_LOGIC
);
END and_gate ;
Digital Electronics & Logic Design ASM
Syntax For ARCHITECTURE BODY
ARCHITECTURE arch_name OF entity_name IS
Local variables / Global Variables / Constants / …..Don’t write anything if not needed
BEGIN
--Your Programming LOGIC
Here you
Mention “ The Logical Relationship between your INPUTS & OUTPUTS”
END arch_name ;
Example of AB For AND Gate
ARCHITECTURE andgate_arch OF and_gate IS
BEGIN
Y < = A and B ;
END arch_name ;
Digital Electronics & Logic Design ASM
The Complete VHDL Program For 4:1 MUX
entity mux41 is
Port
(
I : in std_logic_vector(0 to 3);
s : in std_logic_vector(1 downto 0);
Y : out std_logic
);
end mux41;
architecture mux41_arch of mux41 is
begin
Y <= I(0) when s="00" else
I(1) when s="01" else
I(2) when s="10" else
I(3) ;
end mux41_arch;
Digital Electronics & Logic Design ASM
Architecture
Body
architecture Behavioral of updncounter is
SIGNAL tempcount : STD_LOGIC_VECTOR(2 downto 0); Temporary
begin
Signal
PROCESS( clk , reset , mode )
BEGIN
IF reset='1' THEN
tempcount <= "000" ;
ELSIF clk'event AND clk = '0' THEN
IF mode = '1' THEN
tempcount <= tempcount + 1 ;
ELSE
tempcount <= tempcount - 1 ;
END IF;
END IF;
END PROCESS;
Q <= tempcount;
endDigital Electronics & Logic
Behavioral; ASM
Design
STRUCTURAL Modeli g Style…
carry1
a x1 c1
add1
b x2 s1
cout
sum1
carry2
x1 c1
add2
cin X2 s1 sum
Digital Electronics & Logic
ASM
Design
entity adder is
Port
(
a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
cout : out std_logic
);
end adder ;
architecture adder_arch is
component add is
port
(
x1,x2 : in std_logic;
s1,c1 : out std_logic);
end component;
SIGNAL sum1,carry1,carry2 : std_logic ;
begin
add1 : add port map (x1=>a,x2=>b,c1=>carry1,s1=>sum1);
add2 : add port map (x1=>sum1,x2=>c,c1=>carry2,s1=>sum);
cout<=carry1 OR carry2;
Digital Electronics & Logic
end adder_arch; ASM
Design
Thank You
Digital Electronics & Logic
ASM
Design
