Lecture Series:

Basics of Digital Design at RT Level with Verilog

Z. Navabi

Basics of Digital Design at RT

Level with Verilog

Lecture 1:
Verilog as a Design Tool

July 2014 © 2013-2014 Zain Navabi 1

 Verilog as a Design Tool
—  Simulation
—  Synthesis
—  Language
—  A simulation Environment
—  Summary

July 2014 © 2013-2014 Zain Navabi 2

 Verilog as a Design Tool
Verilog for simulation

July 2014 © 2013-2014 Zain Navabi 3

 Verilog as a Design Tool
Verilog for Synthesis

July 2014 © 2013-2014 Zain Navabi 4

 Verilog as a Design Tool
—  Modules

July 2014 © 2013-2014 Zain Navabi 5

 Verilog as a Design Tool
—  ModelSim simulation environment
◦  Define a project
◦  Enter your design
◦  Generate a testbench providing inputs
◦  Simulate your design
◦  Observe waveforms and outputs
◦  Verify the operation of the design
◦  Finish simulation

July 2014 © 2013-2014 Zain Navabi 6

 Verilog as a Design Tool
—  Summary
◦  Covered terminologies
◦  A simple simulation tool
◦  Became familiar with running the software

July 2014 © 2013-2014 Zain Navabi 7

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 2:
Gate Level Description

July 2014 © 2013-2014 Zain Navabi 8

 Verilog for Gate Level Descriptions

—  Basic Structures of Verilog

—  Levels of Abstraction
—  Combinational Gates
—  Writing Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 9

 Basic Structures of Verilog
—  Modules
—  Module Outline
—  Module Ports
—  Module Variables
—  Wires

July 2014 © 2013-2014 Zain Navabi 10

 Basic Structures of Verilog
—  Modules

July 2014 © 2013-2014 Zain Navabi 11

 Basic Structures of Verilog

—  Modules

July 2014 © 2013-2014 Zain Navabi 12

 Basic Structures of Verilog
—  Module Outline

module name (ports or ports and their declarations);

port declarations if not in the header;
other declarations;
. . .
statements
. . .
endmodule

July 2014 © 2013-2014 Zain Navabi 13

 Basic Structures of Verilog
—  Module Ports

module acircuit (input a, b, output w);

// a comment
// wires and variable declarations
// operation of the circuit
. . .
endmodule

July 2014 © 2013-2014 Zain Navabi 14

 Basic Structures of Verilog
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 15

 Combinational Circuits
—  Gate Level Combinational Circuits

July 2014 © 2013-2014 Zain Navabi 16

 Combinational Circuits
—  Gate Level Combinational Circuits
- Majority Example
- Multiplexer Example

July 2014 © 2013-2014 Zain Navabi 17

 Combinational Circuits
—  Majority Example

July 2014 © 2013-2014 Zain Navabi 18

 Combinational Circuits
—  Majority Example
`timescale 1ns/1ns

module maj3 ( input a, b, c, output y );

wire im1, im2, im3;

and U1 ( im1, a, b );
and U2 ( im2, b, c );
and U3 ( im3, c, a );
or U4 ( y, im1, im2, im3 );

endmodule
Verilog Code for the Majority Circuit

July 2014 © 2013-2014 Zain Navabi 19

 Writing Testbenches
— Apply random data to test maj3
—  Incremental
`timescale data inputs
1ns/1ns

module maj3Tester ();

reg ai=0, bi=0, ci=0;
wire yo;

maj3 MUT ( ai, bi, ci, yo );

initial begin
#23; ai=0; bi=0; ci=1;
#23; ai=1; bi=0; ci=1;
#23; ai=0; bi=0; ci=0;
#23; ai=1; bi=1; ci=1;
#23; ai=0; bi=1; ci=0;
#23; $stop;
end
endmodule

July 2014 © 2013-2014 Zain Navabi 20

 Simulation Results

—  Simulating maj3

July 2014 © 2013-2014 Zain Navabi 21

 Combinational Circuits
—  Multiplexer Example

a
b y `timescale 1ns/1ns

s
module mux_2to1 (a, b, s, y);
input a, b, s;
output y;
wire is;
wire aa, bb;

not U1 (is, s);

and U2 (aa, a, is),
U3 (bb, b, s);
or U4 (y, aa, bb);

endmodule

Multiplexer Schematic

July 2014 © 2013-2014 Zain Navabi 22

 Combinational Circuits
—  Multiplexer Example
`timescale 1ns/1ns

module mux_2to1 (a, b, s, y);

input a, b, s;
output y;
wire is;
wire aa, bb;

not U1 (is, s);

and U2 (aa, a, is),
U3 (bb, b, s);
or U4 (y, aa, bb);
Multiplexer Verilog Code
endmodule

July 2014 © 2013-2014 Zain Navabi 23

 Multiplexer Testbench
—  Apply random test data to test mux
`timescale 1ns/1ns

module muxTester ();

reg ai=0, bi=0, ci=0;
wire yo;

mux_2to1 MUT ( ai, bi, ci, yo );

initial begin
#23; ai=0; bi=0; ci=1;
#23; ai=1; bi=0; ci=1;
#23; ai=0; bi=0; ci=0;
#23; ai=1; bi=1; ci=1;
#23; ai=0; bi=1; ci=0;
#23; $stop;
end
endmodule
July 2014 © 2013-2014 Zain Navabi 24
 Summary
—  The focus of this lecture was on gate level in Verilog
—  Some Basic Verilog concepts were presented
—  We showed examples of levels of abstraction
—  We used Verilog primitives
—  Two examples were used, used somewhat different styles
—  Simple testbenches were used
—  ModelSim simulation run results were shown

July 2014 © 2013-2014 Zain Navabi 25

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 3:
Gate Delays

July 2014 © 2013-2014 Zain Navabi 26

 Gate Delays
—  Switch Level Primitives
—  Logic Value System
—  Transistor (Switch) Level Description
—  Combinational Gates with Delay
—  Three-state Logic
—  Summary

July 2014 © 2013-2014 Zain Navabi 27

 Gate Delays
—  A module using transistors

July 2014 © 2013-2014 Zain Navabi 28

 Basic Structures of Verilog
—  Module Ports

module acircuit (input a, b, output w);

// a comment
// wires and variable declarations
// operation of the circuit using transistors
. . .
endmodule

July 2014 © 2013-2014 Zain Navabi 29

 Basic Structures of Verilog
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 30

 Switch Level Primitives
—  Switches and three-state gates

July 2014 © 2013-2014 Zain Navabi 31

 Switch Level Primitives
—  Logic Value System

◦  0: forced low
◦  1: forced high
◦  Z: open
◦  X: unknown

July 2014 © 2013-2014 Zain Navabi 32

 Transistor (Switch) Level Description
—  CMOS NAND Example

CMOS NAND at the Switch Level

July 2014 © 2013-2014 Zain Navabi 33

 Transistor (Switch) Level Description
—  CMOS NAND Example
`timescale 1ns/1ns

module nand2_1d ( input a, b, output y);

wire im1;
supply1 vdd;
supply0 gnd;
nmos #(3, 4)
g4 (im1, gnd, b),
g3 (y, im1, a);

pmos #(4, 5)
g1 (y, vdd, a),
g2 (y, vdd, b);
endmodule

CMOS NAND Verilog Description

July 2014 © 2013-2014 Zain Navabi 34

 Transistor (Switch) Level Description
—  CMOS NAND Example
`timescale 1ns/1ns

module nand2Tester ();

reg ai=0, bi=0;
wire yo;

nand2_1d MUT ( ai, bi, yo );

initial begin
#25; ai=0; #25; bi=0;
`timescale 1ns/1ns
#25; ai=0; #25; bi=1;
#25; ai=1; #25; bi=0; module nand2_1d ( input a, b, output y);
wire im1;
#25; ai=1; #25; bi=1; supply1 vdd;
supply0 gnd;
#25; ai=0; #25; bi=1; nmos #(3, 4)
g4 (im1, gnd, b),
#25; $stop; g3 (y, im1, a);
end pmos #(4, 5)
endmodule g1 (y, vdd, a),
g2 (y, vdd, b);
endmodule
CMOS NAND Verilog Description

July 2014 © 2013-2014 Zain Navabi 35

 Transistor (Switch) Level Description
—  CMOS NAND Example

CMOS NAND Simulation Result

July 2014 © 2013-2014 Zain Navabi 36

 Transistor (Switch) Level Description
—  Timing analysis

CMOS NAND nmos #(3,4); pmos #(4,5)

July 2014 © 2013-2014 Zain Navabi 37

 Transistor (Switch) Level Description
—  Timing analysis, gate equivalent

CMOS NAND nmos #(3,4); pmos #(4,5)

July 2014 © 2013-2014 Zain Navabi 38

 Three-state Logic
—  Multiplexer Example

July 2014 © 2013-2014 Zain Navabi 39

 Combinational Circuits
—  Multiplexer Example – use three-state gates

`timescale 1ns/1ns

module mux_2to1 ( input a, b, s, output y );

bufif1 #(3) ( y, b, s );
bufif0 #(5) ( y, a, s );

endmodule

Multiplexer Verilog Code

July 2014 © 2013-2014 Zain Navabi 40

 Combinational Circuits
—  Multiplexer Example
`timescale 1ns/1ns

module mux_2to1 (a, b, s, y);

input a, b, s;
output y;
wire is;
wire aa, bb;

not U1 #(3,4) (is, s);

and U2 #(3,4) (aa, a, is),
U3 #(3,4) (bb, b, s);
or U4 #(3,4) (y, aa, bb);
Multiplexer Verilog Code
endmodule

July 2014 © 2013-2014 Zain Navabi 41

 Multiplexer Testbench
—  Random data at some time intervals
`timescale 1ns/1ns

module muxTester ();

reg ai=0, bi=0, ci=0;
wire yo;

mux_2to1 MUT ( ai, bi, ci, yo );

initial begin
#23; ai=0; bi=0; ci=1;
#23; ai=1; bi=0; ci=1;
#23; ai=0; bi=0; ci=0;
#23; ai=1; bi=1; ci=1;
#23; ai=0; bi=1; ci=0;
#23; $stop;
end
endmodule
July 2014 © 2013-2014 Zain Navabi 42
 Multiplexer Testbench
—  Multiplexer output waveform

July 2014 © 2013-2014 Zain Navabi 43

 Summary
—  Discussed the origin of delays
—  Showed 4-value logic value system
—  Performed switch level simulation
—  Simulated gates with delay values
—  ModelSim simulation run results were shown

July 2014 © 2013-2014 Zain Navabi 44

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 4:
Hierarchical Gate Level Design

July 2014 © 2013-2014 Zain Navabi 45

 Hierarchical Gate Level Design
—  Gate Level Design
—  Module Instantiation
—  Top Level Module
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 46

 Hierarchical Gate Level Design

—  Module Hierarchy

July 2014 © 2013-2014 Zain Navabi 47

 Hierarchical Gate Level Design
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 48

 Hierarchical Gate Level Design
—  Module Instantiation

module a_hierarchical_circuit (input a, b, output w);

// a comment
// wires and variable declarations
// operation of the circuit
AnotherTestedModule UUT (port connection according to module being instantiated);
// any number of the above
. . .
endmodule

July 2014 © 2013-2014 Zain Navabi 49

 Basic Structures of Verilog
—  Module Instantiation
◦  Top level design instantiates Majority and Mux

July 2014 © 2013-2014 Zain Navabi 50

 Combinational Circuits
—  Majority Example
`timescale 1ns/1ns

module maj3 ( input a, b, c, output y );

wire im1, im2, im3;

and U1 #(4,5) ( im1, a, b );

and U2 #(4,5) ( im2, b, c );
and U3 #(4,5) ( im3, c, a );
or U4 #(4,5) ( y, im1, im2, im3 );

endmodule
Verilog Code for the Majority Circuit

July 2014 © 2013-2014 Zain Navabi 51

 Combinational Circuits
—  Where delays come from
`timescale 1ns/1ns
module some_circuit ( input a, b, c, output y );
. . .
nand2_ld U1 #(6,8) ( im1, a, b );
. . .
endmodule `timescale 1ns/1ns

module nand2_1d ( input a, b, output y);

wire im1;
supply1 vdd;
supply0 gnd;
nmos #(3, 4)
g4 (im1, gnd, b),
g3 (y, im1, a);

pmos #(4, 5)
g1 (y, vdd, a),
g2 (y, vdd, b);
endmodule

July 2014 © 2013-2014 Zain Navabi 52

 Combinational Circuits
—  Multiplexer Example – use three-state gates

`timescale 1ns/1ns

module mux_2to1 ( input a, b, s, output y );

bufif1 #(3) ( y, b, s );
bufif0 #(5) ( y, a, s );

endmodule

Multiplexer Verilog Code

July 2014 © 2013-2014 Zain Navabi 53

 Hierarchical Gate Level Design
—  Multiplexer Example
`timescale 1ns/1ns

module RateSelector (input a, b, c, d, e, output w);

wire mj;

maj3 U1 (c, d, e, mj);

mux_2to1 U2 (a, b, mj, w);

endmodule

Top level module

July 2014 © 2013-2014 Zain Navabi 54

 Hierarchical Gate Level Design
—  Multiplexer Example
`timescale 1ns/1ns

module RateSelector (input a, b, c, d, e, output w);

wire mj;

maj3 U1 (c, d, e, mj);

mux_2to1 U2 (a, b, mj, w);

endmodule

Top level module

July 2014 © 2013-2014 Zain Navabi 55

 Hierarchical Gate Level Design
—  Periodic data application
`timescale 1ns/1ns

module RateSelectoreTester ();

reg ai=0, bi=0, ci=0, di=0, ei=0;
wire yo;

RateSelector MUT ( ai, bi, ci, di, ei, yo );

always #17 ai = ~ai;

always #33 bi = ~bi;
initial begin
#97; ci=0; di=0; ei=1;
#97; ci=1; di=0; ei=1;
#97; ci=0; di=0; ei=0;
#97; ci=1; di=1; ei=1;
#97; ci=0; di=1; ei=0;
#97; $stop;
end
endmodule
July 2014 © 2013-2014 Zain Navabi 56
 Hierarchical Gate Level Design
—  Selecting one of the two frequencies

July 2014 © 2013-2014 Zain Navabi 57

 Summary

—  Talked about module hierarchy

—  Any design can have a hierarchy and instantiation of other
modules
—  The design remains at the gate level
—  Talked about more constructs to use in a testbench

July 2014 © 2013-2014 Zain Navabi 58

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 5:
Using Expressions in Modules

July 2014 © 2013-2014 Zain Navabi 59

 Using Expressions in Modules
—  Boolean expressions
—  Two familiar examples
—  Module Instantiation
—  Top Level Module
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 60

 Boolean Expressions

—  Use Verilog assign statement

—  assign statements in a module are considered as logic
blocks
—  Position in module code is irrelevant
—  Use the following notations:
◦  For AND use: &
◦  For OR use: |
◦  For NOT use: ~
◦  For XOR use: ^
◦  Use parenthesis for enforcing precedence

July 2014 © 2013-2014 Zain Navabi 61

 Boolean Expressions

—  Use Verilog assign statement

—  Format: assign #(0 to1_Delay, 1to0_Delay) w = a & b & c;

assign #(Delay) w = a & b & c;
assign #Delay w = a & b & c;
assign w = a & b & c;

—  Optional delay parameters

—  Output is w
—  Inputs are a, b, c

July 2014 © 2013-2014 Zain Navabi 62

 Boolean Expressions
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 63

 Boolean Expressions
—  From KM
◦  A circuit that produces a 1 if abcd is divisible by 3 or 4
◦  Input is abcd and treated as a 4-bit binary number
◦  Assume non-zero input

July 2014 © 2013-2014 Zain Navabi 64

 Boolean Expressions

module div3or4 (input a, b, c, d, output w);

assign w = (~c & ~d) |

(a & ~b & ~c) |
(~a & ~b & c & d) |
(~a & b & ~d) |
(a & b & c & d);

endmodule

July 2014 © 2013-2014 Zain Navabi 65

 Boolean Expressions
—  From KM
◦  A circuit that produces a 1 if abcd is divisible by 3 or 5
◦  Input is abcd and treated as a 4-bit binary number
◦  It turns out that output is 1 if even number of 1’s are in abcd

July 2014 © 2013-2014 Zain Navabi 66

 Boolean Expressions
—  Module Description

module div3or5 (input a, b, c, d, output w);

assign #(68,70) w = ~a ^ b ^ c ^ d;

endmodule

July 2014 © 2013-2014 Zain Navabi 67

 Boolean Expressions

—  Where delays come from?

July 2014 © 2013-2014 Zain Navabi 68

 Two Familiar Examples
—  Module Instantiation
◦  Top level design instantiates Majority and Mux

July 2014 © 2013-2014 Zain Navabi 69

 Two Familiar Examples
—  Majority Example

`timescale 1ns/1ns

module maj3 ( input a, b, c, output y );

assign y = (a & b) | (a & c) | (b & c);

endmodule

Verilog Code for the Majority Circuit

July 2014 © 2013-2014 Zain Navabi 70

 Two Familiar Examples
—  Multiplexer Example – Use AND OR gates

`timescale 1ns/1ns

module mux_2to1 ( input a, b, s, output y );

assign #(5) y = (a & ~s) | (b & s);

endmodule

Verilog Code for the Multiplexer

July 2014 © 2013-2014 Zain Navabi 71

 Two Familiar Examples
—  Multiplexer Example – Use three-state gates

`timescale 1ns/1ns

module mux_2to1 ( input a, b, s, output y );

assign #(5) y = ~s ? a : b;

endmodule

Multiplexer Verilog Code

July 2014 © 2013-2014 Zain Navabi 72

 Hierarchical Expression Level Design
—  Rate Selector Example
`timescale 1ns/1ns

module RateSelector (input a, b, c, d, e, output w);

wire mj;

maj3 U1 (c, d, e, mj);

mux_2to1 U2 (a, b, mj, w);

endmodule

Top level module

July 2014 © 2013-2014 Zain Navabi 73

 Multiple Expressions
—  Rate Selector Example
`timescale 1ns/1ns

module RateSelector (input a, b, c, d, e, output w);

wire mj;

assign mj = (c & d) | (c & e) | (d & e);

assign #(5) w = (a & ~mj) | (b & mj);

endmodule

Module with two expressions

July 2014 © 2013-2014 Zain Navabi 74

 Hierarchical Expression Level Design
—  Periodic data application
`timescale 1ns/1ns

module RateSelectoreTester ();

reg ai=0, bi=0, ci=0, di=0, ei=0;
wire yo;

RateSelector MUT ( ai, bi, ci, di, ei, yo );

always #17 ai = ~ai;

always #33 bi = ~bi;
initial begin
#97; ci=0; di=0; ei=1;
#97; ci=1; di=0; ei=1;
#97; ci=0; di=0; ei=0;
#97; ci=1; di=1; ei=1;
#97; ci=0; di=1; ei=0;
#97; $stop;
end
endmodule
July 2014 © 2013-2014 Zain Navabi 75
 Summary

—  Expression in Verilog

—  Assignments from Boolean
—  Use of assign statements
—  Multiple assignments
—  Delay values
—  Two versions of Rate Selector

July 2014 © 2013-2014 Zain Navabi 76

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 6:
Timing and Dynamic Hazards

July 2014 © 2013-2014 Zain Navabi 77

 Timing and Static Hazards
—  Hazards
—  Multiplexer Example
—  Hazards on Karnaugh Maps
—  Preventing Hazards
—  Four Variable Example
—  Summary

July 2014 © 2013-2014 Zain Navabi 78

 Hazards

—  Change in one input

—  1-Hazard
◦  Should be 1, but a 0-glitch
—  0-Hazard
◦  Should be 0, but a 1-glitch

July 2014 © 2013-2014 Zain Navabi 79

 Multiplexer Example
—  Multiplexer Example – Using AND OR gates

`timescale 1ns/1ns

module mux2to1 ( input a, b, s, output y );

wire sn, asn, bs;

not #7 (sn, s);

and #4 (asn, a, sn);
and #4 (bs, b, s);
or #3 (y, asn, bs);

endmodule
Verilog Code for the Multiplexer

July 2014 © 2013-2014 Zain Navabi 80

 Multiplexer Example
—  Multiplexer Testbench
`timescale 1ns/1ns
Verilog Code for the Multiplexer
module mux2to1Tester ();
reg ai=0, bi=0, si=0;
wire yo;

mux_2to1 MUT ( ai, bi, si, yo );

initial begin
#29; ai=1; bi=0; si=0;
#29; ai=1; bi=1; si=0;
#29; ai=1; bi=1; si=1;
#29; ai=1; bi=1; si=0;
#29; ai=1; bi=1; si=1;
#29; $stop;
end
endmodule
July 2014 © 2013-2014 Zain Navabi 81
 Multiplexer Example

July 2014 © 2013-2014 Zain Navabi 82

 Multiplexer Example
—  Hazard Correction K-Map

July 2014 © 2013-2014 Zain Navabi 83

 Preventing Hazards
—  Map adjacent 1’s in AND-OR circuits
—  Map adjacent 0’s in OR-AND circuits

July 2014 © 2013-2014 Zain Navabi 84

 Four Variable Maps
—  From KM
◦  Show circuit
◦  Add gates to remove hazards

July 2014 © 2013-2014 Zain Navabi 85

 Four Variable Maps
—  From KM
◦  Show circuit
◦  Add gates to remove hazards

July 2014 © 2013-2014 Zain Navabi 86

 Four Variable Maps

module HazardNotSeen (input a, b, c, d, output w);

assign w = (~c & ~d) |

(a & d) |
(~a & b & c);

endmodule

July 2014 © 2013-2014 Zain Navabi 87

 Summary

—  Hazards
—  Multiplexer Example
—  Hazards on Karnaugh Maps
—  Preventing Hazards
—  Four Variable Example
—  Summary

July 2014 © 2013-2014 Zain Navabi 88

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 7:
Arithmetic Circuits

July 2014 © 2013-2014 Zain Navabi 89

 Arithmetic Circuits
—  New operations
—  Full adder
—  Vector inputs
—  Structural adder
—  Adder using expressions
—  A multi-function module
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 90

 New Operations

—  Use Verilog assign statement

—  Position in module code is irrelevant
—  Use the following notations:
◦  For Adding use: +
◦  For Subtracting use: -
◦  For Comparing use: < > <= >= ==
◦  For Condition use: ?:
◦  For Concatenation use: {}
◦  Use parenthesis for enforcing precedence

July 2014 © 2013-2014 Zain Navabi 91

 New Operation

—  Use Verilog assign statement

—  Format: assign w = a + b;
assign w = a -b
assign w = (f==1) ? y : z;
assign w = (a > b) ? a : b;
—  Vector format [7:0]
—  Output is w and is a vector, e.g., w[7:0]
—  Inputs are a, b, f
◦  a and b are vectors
◦  f is a scalar

July 2014 © 2013-2014 Zain Navabi 92

 New Operations
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 93

 Full Adder
—  Descriptions by Use of Equations
- Sum output

`timescale 1ns/1ns

module xor3 ( input a, b, c, output y );

assign y = a ^ b ^ c;
endmodule

XOR Verilog Code

July 2014 © 2013-2014 Zain Navabi 94

 Full Adder
—  Descriptions by Use of Equations
- Carry output

`timescale 1ns/1ns

module maj3 ( input a, b, c, output y );

assign y = (a & b) | (a & c) | (b & c);
endmodule

Majority Verilog Code

July 2014 © 2013-2014 Zain Navabi 95

 Full Adder
—  Descriptions by Use of Equations
- Full-Adder Example
`timescale 1ns/1ns

module fulladder ( input a, b, ci, output s, co );

assign #(10) s = a ^ b ^ ci;
assign #(8) co = ( a & b ) | ( b & ci ) | ( a &
ci );
endmodule

Full Adder Verilog Code

July 2014 © 2013-2014 Zain Navabi 96

 Structural Adder
—  A simpler design of full-adder
—  Using 8 full-adders to build an 8-bit adder

Slow
Adder
July 2014 © 2013-2014 Zain Navabi 97
 Structural Adder
—  Descriptions by Use of Equations
- Full-Adder using fewer gates
`timescale 1ns/1ns

module fulladder ( input a, b, ci, output s, co );

wire axb;
assign axb = a ^ b;
assign s = axb ^ ci;
assign co = ( a & b ) | ( axb & ci );
endmodule

Full Adder Verilog Code

July 2014 © 2013-2014 Zain Navabi 98

 Structural Adder
—  Instantiate 8 full-adders
`timescale 1ns/1ns

module adder8 ( input [7:0] a, b, input ci,

output [7:0] s, output co );
wire [7:0] c;
assign c[0] = ci;
fulladder FA0 (a[0], b[0], c[0], s[0], c[1]);
fulladder FA1 (a[1], b[1], c[1], s[1], c[2]);
fulladder FA2 (a[2], b[2], c[2], s[2], c[3]);
fulladder FA3 (a[3], b[3], c[3], s[3], c[4]);
fulladder FA4 (a[4], b[4], c[4], s[4], c[5]);
fulladder FA5 (a[5], b[5], c[5], s[5], c[6]);
fulladder FA6 (a[6], b[6], c[6], s[6], c[7]);
fulladder FA7 (a[7], b[7], c[7], s[7], co);
endmodule

Eight-bit Adder Verilog Code

July 2014 © 2013-2014 Zain Navabi 99
 Adder Using Expressions
—  Use assign statement and concatenation

`timescale 1ns/1ns

module adder8 ( input [7:0] a, b, input ci,

output [7:0] s, output co );

assign {co, s} = a + b + ci;

endmodule

Eight-bit Functional Adder Verilog Code

July 2014 © 2013-2014 Zain Navabi 100

 Multi Function Modules
—  Descriptions by Use of Equations
- ALU Example

module ALU ( input [7:0] a, b, input addsub,

output gt, zero, co, output [7:0] r );

assign {co, r} = addsub ? (a + b) : (a – b);

assign gt = (a>b);
assign zero = (r == 0);
endmodule

ALU Verilog Code Using a Mix of Operations

July 2014 © 2013-2014 Zain Navabi 101

 Testbenches
—  Use initial repeat

`timescale 1ns/1ns

module adder8testbench ();

reg [7:0] ai, bi;

reg ci=0;
wire [7:0] so;
wire co;

adder8 UUT (ai, bi, ci, so, co);

initial repeat (20) #17 ai = $random;
initial repeat (16) #23 bi = $random;

endmodule

Eight-bit Adder Verilog Testbench

July 2014 © 2013-2014 Zain Navabi 102

 Testbenches
—  Simulation results

July 2014 © 2013-2014 Zain Navabi 103

 Summary

—  New operations

—  Full adder
—  Vector inputs
—  Structural adder
—  Adder using expressions
—  A multi-function module
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 104

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 8:
Behavioral Modeling

July 2014 © 2013-2014 Zain Navabi 105

 Behavioral Modeling
—  New constructs
◦  Procedural blocks
◦  Procedural statements
—  Procedural always block
◦  Majority circuit
◦  Full adder
—  Delay options
—  Procedural statements
—  A behavioral ALU
—  Summary

July 2014 © 2013-2014 Zain Navabi 106

 New Constructs

—  Use Verilog always statement

—  Position of various always statements in module code is
irrelevant
—  Position of statements within an always statements is
important

July 2014 © 2013-2014 Zain Navabi 107

 New Constructs

—  Use the following constructs:

◦  Procedural if: if (a==b) DoThis else DoThat;
◦  Procedural if: if (a==b) begin . . . end
else begin . . . end
◦  Procedural case: case (expr)
0: …
1: . . .
2: . . .
endcase

July 2014 © 2013-2014 Zain Navabi 108

 New Operations
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 109

 Procedural always Block
—  XOR example

`timescale 1ns/1ns

module xor3 ( input a, b, c,

output reg y );

always @(a, b, c) y = a ^ b ^ c;

endmodule

XOR Verilog Code

July 2014 © 2013-2014 Zain Navabi 110

 Procedural always Block
—  Majority Example

module maj3 ( input a, b, c, output reg y );

always @( a or b or c )
begin
y = (a & b) | (b &c) | (a & c);
end

endmodule

Procedural Block Describing a Majority Circuit

July 2014 © 2013-2014 Zain Navabi 111

 Delay Options
—  Majority example with delay

`timescale 1ns/100ps

module maj3 ( input a, b, c, output reg y );

always @(a, b, c )
#5 y = (a & b) | (b &c) | (a & c);

endmodule

Majority Gate with Delay

July 2014 © 2013-2014 Zain Navabi 112

 Delay Options
—  Descriptions with procedural statements
- Full-Adder example
`timescale 1ns/100ps
module add_1bit ( input a, b, ci,
output reg s, co );

always @( a, b, ci )
begin
s = #5 a ^ b ^ ci;
co = #3 (a & b) | (b &ci) | (a & ci);
end

endmodule
Full-Adder Using Procedural Assignments
July 2014 © 2013-2014 Zain Navabi 113
 Delay Options
—  Descriptions with procedural statements
- Full-Adder example
`timescale 1ns/100ps
module add_1bit ( input a, b, ci,
output reg s, co );

always @( a, b, ci )
begin
s <= #5 a ^ b ^ ci;
co <= #8 (a & b) | (b &ci) | (a & ci);
end

endmodule
Full-Adder Using Procedural Assignments
July 2014 © 2013-2014 Zain Navabi 114
 Procedural Statements
—  Descriptions with Procedural Statements
- Procedural Multiplexer Example

module mux2_1 (input i0, i1, s, output reg y );

always @( i0 or i1 or s ) begin
if ( s==1'b0 )
y = i0;
else
y = i1;
end
endmodule

Procedural Multiplexer

July 2014 © 2013-2014 Zain Navabi 115

 Procedural Statements
—  Descriptions with Procedural Statements
- Procedural ALU Example
module alu_4bit (input [3:0] a, b, input [1:0] f,
output reg [3:0] y );
always @ ( a or b or f ) begin
case ( f )
2'b00 : y = a + b;
2'b01 : y = a - b;
2'b10 : y = a & b;
2'b11 : y = a ^ b;
default: y = 4'b0000;
endcase
end
endmodule

Procedural ALU

July 2014 © 2013-2014 Zain Navabi 116

 Summary
—  New constructs
◦  Procedural blocks
◦  Procedural statements
—  Procedural always block
◦  Majority circuit
◦  Full adder
—  Delay options
—  Procedural statements
—  A behavioral ALU
—  Summary

July 2014 © 2013-2014 Zain Navabi 117

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 9:
Flip-Flop Modeling

July 2014 © 2013-2014 Zain Navabi 118

 Flip-flop Modeling
—  New constructs
◦  Procedural blocks
◦  Posedge
◦  Nonblocking assignment
—  Edge sensitive always block
◦  Clock edge
◦  Asynchronous control
◦  Clock enable
—  Delay options
—  D-type flip-flop
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 119

 New Constructs

—  Use Verilog always statement

—  Position of various always statements in module code is
irrelevant
—  Use posedge or negedge for edge
—  Position of statements within an always statements is
important
—  Check for flip-flop functions according to their priority
—  Assign flip-flop output using <=

July 2014 © 2013-2014 Zain Navabi 120

 Edge Sensitive always Block

—  Use in the following forms:

◦  Clock detection: always @(posedge C) begin
Q <= D;
end
◦  Clock detection: always @(posedge C) Q <= D;
◦  Asynch reset: always @(posedge C, posedge R) begin
if (R) Q <= 0;
...
end
◦  Clock enable: always @(posedge C) if (E) Q <= D;

July 2014 © 2013-2014 Zain Navabi 121

 Flip-flop Modeling
—  Module Outline

July 2014 © 2013-2014 Zain Navabi 122

 Delay Options
—  Delay after edge of C, before reading D, before
scheduling into Q
#6 Q <= D

—  Delay after edge of C, does not affect reading D, delay

scheduling D into Q
Q <= #5 D

—  After edge of C, wait 5, read D, wait 6, Q gets D

#6 Q <= #5 D

July 2014 © 2013-2014 Zain Navabi 123

 D-type flip-flop
—  Basic D-type flip-flop

`timescale 1ns/1ns

module basic_dff ( input d, clk,

output reg q, output q_b );

always @( posedge clk ) begin

#4 q <= d;
end

assign #3 q_b = ~q;

endmodule
A Positive-Edge D Flip-Flop

July 2014 © 2013-2014 Zain Navabi 124

 D-type flip-flop
—  D-type flip-flop with reset input

`timescale 1ns/1ns

module dff_reset ( input d, clk, reset

output reg q);

always @( posedge clk, posedge reset ) begin

if (reset) q <= 1’b0;
else q <= d;
end

endmodule
A Positive-Edge D Flip-Flop with active high reset

July 2014 © 2013-2014 Zain Navabi 125

 D-type flip-flop
—  D-type flip-flop with reset input

`timescale 1ns/1ns

module dff_reset ( input d, clk, reset

output reg q);

always @( posedge clk, negedge reset ) begin

if (~reset) q <= 1’b0;
else q <= d;
end

endmodule
A Positive-Edge D Flip-Flop with active low reset

July 2014 © 2013-2014 Zain Navabi 126

 D-type flip-flop
—  Memory Elements Using Procedural Statements
- Asynchronous Control

s s
q q
d d
clk q_b clk q_b
r r

July 2014 © 2013-2014 Zain Navabi 127

 D-type flip-flop
—  D-type flip-flop with set and reset input

`timescale 1ns/1ns

module dff_reset ( input d, clk, set, reset

output reg q);

always @(posedge clk, posedge reset, posedge set)

if (reset) q <= 1’b0;
else if (set) q <= 1’b1;
else q <= d;

endmodule

A Positive-Edge D Flip-Flop with active high set and reset

July 2014 © 2013-2014 Zain Navabi 128

 D-type flip-flop
—  D-type flip-flop with clock enable

`timescale 1ns/1ns

module dff_enable ( input d, clk, en,

output reg q);

always @(posedge clk)

if (en) q <= d;

endmodule

A Positive-Edge D Flip-Flop with active high enable

July 2014 © 2013-2014 Zain Navabi 129

 More on Testbenches
—  Apply periodic clock `timescale 1ns/1ns

`timescale 1ns/1ns module dff_enable (input d, clk, en,

output reg q);

module dffTester (); always @(posedge clk)

reg di=0, clki=0, eni=0; if (en) q <= d;

wire qo; endmodule

dff_enable MUT ( di, clki, eni, qo );

always #29 clki = ~ clki;

initial begin
#23 di=0; #37 di=1; #23 di=0; #37 di=1;
#23 di=0; #37 di=1; #23 di=0; #37 di=1;
$stop;
end

initial begin #37 eni=1; #187 eni=0; end

endmodule

July 2014 © 2013-2014 Zain Navabi 130

 Summary
—  New constructs
◦  Procedural blocks
◦  Posedge
◦  Nonblocking assignment
—  Edge sensitive always block
◦  Clock edge
◦  Asynchronous control
◦  Clock enable
—  Delay options
—  D-type flip-flop
—  More on Testbenches
—  Summary

July 2014 © 2013-2014 Zain Navabi 131

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 10:
Elements of RT Level Design

July 2014 © 2013-2014 Zain Navabi 132

 Outline
—  RTL Big Picture View
—  Processing Elements
—  Bussing System
—  Controller
—  Summary

July 2014 © 2013-2014 Zain Navabi 133

 RTL Big Picture View
—  Datapath
-  Combinational elements
-  Sequential elements
-  Bussing structure
—  Controller
-  State machines

July 2014 © 2013-2014 Zain Navabi 134

 Processing Elements
Ain
S
•  Combinational elements Bin
Cin FA Co

Comprator aLtb
B

•  Sequential elements

UpCounter count

Rst CounterEn
CLK

July 2014 © 2013-2014 Zain Navabi 135

 Bussing System:
Intra RTL Communication

•  Bussing structure
Controller

ALU
Register  File

Shared  Bus
Data  
Memory

Instruction
Memory

Divider

July 2014 © 2013-2014 Zain Navabi 136

 Controller:

•  State machines
- Mealy/ Moore
- Huffman coding style

July 2014 © 2013-2014 Zain Navabi 137

 Outline
—  RTL Big Picture View
—  Processing Elements
—  Bussing System
—  Controller
—  Summary

July 2014 © 2013-2014 Zain Navabi 138

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 11:
Combinational Elements of RTL
Design
(Datapath building blocks)
July 2014 © 2013-2014 Zain Navabi 139
 Combinational Elements of RTL Design
—  Logic units, arithmetic units, busses
- Random logic
- Iterative hardware
- Bussing system
- General logic units

July 2014 © 2013-2014 Zain Navabi 140

 Random logic
—  A Boolean expression example

module someLogic ( input a, b, c, d, output y );

assign y = ((a&b) | (b&c) | (a&c)) ^ d;

endmodule

A concurrent assign statement

July 2014 © 2013-2014 Zain Navabi 141

 Random logic
—  A conditional expression example

module sameLogic ( input a, b, c, d, output y );

assign y = d ? ~((a&b) | (b&c) | (a&c)) :

((a&b) | (b&c) | (a&c));

endmodule

A concurrent assign statement

July 2014 © 2013-2014 Zain Navabi 142

 Iterative logic
—  32-bit ripple carry adder

b31 a31 b2 a2 b1 a1 b0 a0

Full  Adder Full  Adder Full  Adder Full  Adder

Cin
Cout
S31 S2 S1 S0

July 2014 © 2013-2014 Zain Navabi 143

 Iterative logic
—  8-bit ripple carry adder, 8 instantiations

July 2014 © 2013-2014 Zain Navabi 144

 Iterative logic
—  32-bit ripple carry adder, generate

July 2014 © 2013-2014 Zain Navabi 145

 Bussing system
—  A three-bus system
module bussingSystem (input [7:0] abus, bbus, cbus,
input sa, sb, sc,
output [7:0] ybus );

assign ybus = sa ? abus : 8’bz;

assign ybus = sb ? bbus : 8’bz;
assign ybus = sc ? cbus : 8’bz;

endmodule

Using assign statements

July 2014 © 2013-2014 Zain Navabi 146

 General logic units
—  An ALU with flags
module alu_8bit (input [7:0] a, b, input [1:0] f,
output gt, zero,
output reg [7:0] y );
always @ ( a, b, f ) begin
case ( f )
2'b00 : y = a + b;
2'b01 : y = a>b ? a ? b;
2'b10 : y = a & b;
2'b11 : y = a ^ b;
default: y = 4'b0000;
endcase
Procedural
end ALU
assign gt = a > b;
assign zero = (y==8’b0) ? 1’b1 : 1’b0;
endmodule

July 2014 © 2013-2014 Zain Navabi 147

 Summary

—  Logic units, arithmetic units, busses

—  Random logic
—  Iterative hardware
—  Bussing system
—  General logic units

July 2014 © 2013-2014 Zain Navabi 148

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 12:
Sequential Elements of RTL Design

July 2014 © 2013-2014 Zain Navabi 149

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters
- Registers
- Shift-Register
- Counters

July 2014 © 2013-2014 Zain Navabi 150

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters - Registers

module register (input [7:0] d, input clk, set, reset,

output reg [7:0] q);
always @ ( posedge clk ) begin
if ( set )
#5 q <= 8'b1;
else if ( reset )
#5 q <= 8'b0;
else
#5 q <= d;
end
endmodule

An 8-bit Register

July 2014 © 2013-2014 Zain Navabi 151

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters - Shift-Registers

module shift_reg (input [3:0] d, input clk, ld, rst,

l_r, s_in, output reg [3:0] q);
always @( posedge clk ) begin
if ( rst )
#5 q <= 4'b0000;
else if ( ld )
#5 q <= d;
else if ( l_r )
#5 q <= {q[2:0], s_in};
else
#5 q <= {s_in, q[3:1]};
end
endmodule
A 4-bit Shift Register

July 2014 © 2013-2014 Zain Navabi 152

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters - Shift-Registers

July 2014 © 2013-2014 Zain Navabi 153

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters - Shift-Registers
module shift_reg (input [3:0] d_in, input clk, input [1:0]
s_cnt, sr, sl, ld, output reg [3:0] q );
reg [3:0] int_q;
always @(d_in, s_cnt, sr, sl, ld, q) begin:combinational
if ( ld ) int_q = d_in;
else if ( sr ) int_q = q >> s_cnt;
else if ( sl ) int_q = q << s_cnt;
else int_q = q;
end
always @ ( posedge clk ) begin:register
q <= int_q;
end
endmodule
Shift-Register Using Two Procedural Blocks

July 2014 © 2013-2014 Zain Navabi 154

 Sequential Elements of RTL Design
—  Registers, Shifters and Counters - Counters
module counter (input [3:0] d_in, input clk, rst, ld,
u_d, output reg [3:0] q );
always @ ( posedge clk ) begin
if ( rst )
q <= 4'b0000;
else if ( ld )
q <= d_in;
else if ( u_d )
q <= q + 1;
else
q <= q - 1;
end
endmodule
An Up-Down Counter

July 2014 © 2013-2014 Zain Navabi 155

 Sequential Elements of RTL Design
—  Synthesis of Shifters and Counters

July 2014 © 2013-2014 Zain Navabi 156

 Summary

—  Sequential Elements

—  Registers
—  Counters
—  Shift registers

July 2014 © 2013-2014 Zain Navabi 157

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 13:
State Machines
(Controller building blocks)

July 2014 © 2013-2014 Zain Navabi 158

 State Machines
—  State Machine Coding
- Moore Detector
- A Mealy Machine Example
- Huffman Coding Style
- More Complex Outputs

July 2014 © 2013-2014 Zain Navabi 159

 State Machines
—  State Machine Coding

July 2014 © 2013-2014 Zain Navabi 160

 State Machines
—  State Machine Coding - Moore Detector
module moore_detector (input x, rst, clk, output z);
parameter [1:0] reset = 0, got1 = 1, got10 = 2, got101 = 3;
reg [1:0] current;
always @ ( posedge clk ) begin
if ( rst ) begin
current <= reset;
end
else case ( current )
reset: begin
if ( x==1'b1 ) current <= got1;
else current <= reset;
end
got1: begin
if ( x==1'b0 ) current <= got10;
else current <= got1;
end
Moore Machine Verilog Code . . .

July 2014 © 2013-2014 Zain Navabi 161

 State Machines
—  State Machine Coding - Moore Detector
got10: begin
if ( x==1'b1 ) begin
current <= got101;
end else begin
current <= reset;
end
end
got101: begin
if ( x==1'b1 ) current <= got1;
else current <= got10;
end
default: current <= reset;
endcase
end
assign z = (current == got101) ? 1 : 0;
endmodule
. . . Moore Machine Verilog Code

July 2014 © 2013-2014 Zain Navabi 162

 State Machines
—  State Machine Coding
- Moore Detector

case ( current )
reset: begin . . . end
got1: begin . . . end
got10: begin . . . end
got101: begin . . . end
default: begin . . . end
endcase

case-Statement Outline

July 2014 © 2013-2014 Zain Navabi 163

 State Machines
—  State Machine Coding
- Moore Detector

July 2014 © 2013-2014 Zain Navabi 164

 State Machines
—  State Machine Coding
- A Mealy Machine Example

July 2014 © 2013-2014 Zain Navabi 165

 State Machines
—  State Machine Coding - A Mealy Machine Example
module mealy_detector ( input x, clk, output z );
parameter [1:0]
reset = 0, // 0 = 0 0
got1 = 1, // 1 = 0 1
got10 = 2; // 2 = 1 0
reg [1:0] current;
initial current = reset;
always @ ( posedge clk )
begin
case ( current )
reset:
if( x==1'b1 ) current <= got1;
else current <= reset;
got1:
if( x==1'b0 ) current <= got10;
else current <= got1;
Verilog Code of 101 Mealy Detector . . .

July 2014 © 2013-2014 Zain Navabi 166

 State Machines
—  State Machine Coding - A Mealy Machine Example

got10:
if( x==1'b1 ) current <= got1;
else current <= reset;
default: current <= reset;
endcase
end
assign z= ( current==got10 && x==1'b1 ) ? 1'b1 : 1'b0;

endmodule
. . . Verilog Code of 101 Mealy Detector

July 2014 © 2013-2014 Zain Navabi 167

 State Machines
—  State Machine Coding
- Huffman Coding Style

July 2014 © 2013-2014 Zain Navabi 168

 State Machines
—  State Machine Coding
- Huffman Coding Style

July 2014 © 2013-2014 Zain Navabi 169

 State Machines
—  State Machine Coding - More Complex Outputs
module moore_detector ( input x, rst, clk, output z );
parameter [1:0] reset = 2'b00, got1 = 2'b01,
got10 = 2'b10, got101 = 2'b11;
reg [1:0] p_state, n_state;

always @ ( p_state or x ) begin : combinational

n_state = 0;
case ( p_state )
reset: begin
if( x==1'b1 ) n_state = got1;
else n_state = reset;
end
got1: begin
if( x==1'b0 ) n_state = got10;
else n_state = got1;
end
Verilog Huffman Coding Style . . .

July 2014 © 2013-2014 Zain Navabi 170

 State Machines
—  State Machine Coding - More Complex Outputs

got101: begin
if( x==1'b1 ) n_state = got1;
else n_state = got10;
end
default: n_state = reset;
endcase
end

. . . Verilog Huffman Coding Style . . .

July 2014 © 2013-2014 Zain Navabi 171

 State Machines
—  State Machine Coding - More Complex Outputs

always @( posedge clk ) begin : register

if( rst ) p_state = reset;
else p_state = n_state;
end

assign z = (current == got101) ? 1 : 0;

endmodule

. . . Verilog Huffman Coding Style

July 2014 © 2013-2014 Zain Navabi 172

 State Machines
—  State Machine Coding - More Complex Outputs
module mealy_detector ( input x, en, clk, rst, output reg z );
parameter [1:0] reset = 0,
got1 = 1, got10 = 2, got11 = 3;
reg [1:0] p_state, n_state;

always @( p_state or x ) begin : Transitions

. . .
end
always @( p_state or x ) begin: Outputting
. . .
end
always @ ( posedge clk ) begin: Registering
. . .
end
endmodule
Separate Transition and Output Blocks . . .

July 2014 © 2013-2014 Zain Navabi 173

 State Machines
—  State Machine Coding - More Complex Outputs
always @( p_state or x ) begin : Transitions
n_state = reset;
case ( p_state )
reset:
if ( x == 1'b1 ) n_state = got1;
else n_state = reset;
got1:
if ( x == 1'b0 ) n_state = got10;
else n_state = got11;
got10:
if ( x == 1'b1 ) n_state = got1;
else n_state = reset;
got11:
if ( x == 1'b1 ) n_state = got11;
else n_state = got10;
default: n_state = reset;
endcase
end
. . . Separate Transition and Output Blocks . . .

July 2014 © 2013-2014 Zain Navabi 174

 State Machines
—  State Machine Coding - More Complex Outputs

always @( p_state or x ) begin: Outputting

z = 0;
case ( p_state )
reset: z = 1'b0;
got1: z = 1'b0;
got10: if ( x == 1'b1 ) z = 1'b1;
else z = 1'b0;
got11: if ( x==1'b1 ) z = 1'b0;
else z = 1'b1;
default: z = 1'b0;
endcase
end
. . . Separate Transition and Output Blocks . . .

July 2014 © 2013-2014 Zain Navabi 175

 State Machines
—  State Machine Coding - More Complex Outputs

always @ ( posedge clk ) begin: Registering

if( rst ) p_state <= reset;
else if( en ) p_state <= n_state;
end

. . . Separate Transition and Output Blocks

July 2014 © 2013-2014 Zain Navabi 176

 State Machines
—  State Machine Synthesis

July 2014 © 2013-2014 Zain Navabi 177

 Summary

—  State Machine Coding

- Moore Detector
- A Mealy Machine Example
- Huffman Coding Style
- More Complex Outputs

July 2014 © 2013-2014 Zain Navabi 178

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 14:
Memories
(Used in RTL Datapath)

July 2014 © 2013-2014 Zain Navabi 179

 Memories
—  Memory declaration
—  Memory part selection
—  Memory module
—  Summary

July 2014 © 2013-2014 Zain Navabi 180

 Memories
—  Memory declaration

reg [7:0] a_array [0:1023][0:511];

reg [7:0] Areg; // An 8-bit vector

reg Amem [7:0]; // A memory of 8 1-bit elements
reg Dmem [7:0][0:3]; // 2-Dim mem, 1-bit elements
reg [7:0] Cmem [0:3]; // A memory of four 8-bit words
reg [2:0] Dmem [0:3][0:4]; // 2-Dim mem, 3-bit elements
reg [7:0] Emem [0:1023]; // A memory of 1024 8-bit words

Array Declaration Examples

July 2014 © 2013-2014 Zain Navabi 181

 Memories
—  Memory part selection
- Array Indexing

Areg [5:3] selects bits 5, 4, and 3

Areg [5-:4] selects bits 5, 4, 3, and 2
Areg [2+:4] selects bits 5, 4, 3, and 2
 
 
Cmem [Areg[7:6]] // extracts Cmem word
// addressed by Areg[7:6]
 
 
Emem [Emem[0]] // extracts Emem word
// addressed by Emem[0]
 

July 2014 © 2013-2014 Zain Navabi 182

 Memories
—  Memory part selection
- Array Indexing

 
Emem [355][3:0] // 4 LSB of location 355

 
Emem [355][3-:4] // 4 bits starting from 3, down
 

Emem [355:358] // Illegal.

// This is not a 4-word block

Dmem [0][2]58] // Illegal.

// This is not a 4-word block

July 2014 © 2013-2014 Zain Navabi 183

 Memories
—  Memory module
- Standard clocked register file

module memory (input [7:0] inbus,

output [7:0] outbus,
input [9:0] addr, input clk, rw);
reg [7:0] mem [0:1023];
assign outbus = rw ? mem [addr] : 8'bz;
always @ (posedge clk)
if (rw == 0) mem [addr] = inbus;
endmodule

Memory Description

July 2014 © 2013-2014 Zain Navabi 184

 Summary
—  Memory declaration
—  Memory part selection
—  Memory module
—  Summary

July 2014 © 2013-2014 Zain Navabi 185

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 15:
Writing Testbenches

July 2014 © 2013-2014 Zain Navabi 186

 Writing Testbenches
—  Periodic data
—  Random data
—  Timed data
—  Summary

July 2014 © 2013-2014 Zain Navabi 187

 Writing Testbenches
—  Generating Periodic Data
—  Random Input Data
—  Timed Data
module moore_detector ( input x, rst, clk, output z );
parameter [1:0] a=0, b=1, c=2, d=3;
reg [1:0] current;
always @( posedge clk )
if ( rst ) current = a;
else case ( current )
a : current <= x ? b : a ;
b : current <= x ? b : c ;
c : current <= x ? d : a ;
d : current <= x ? b : c ;
default : current <= a;
endcase
assign z = (current==d) ? 1'b1 : 1'b0;
endmodule
Circuit Under Test

July 2014 © 2013-2014 Zain Navabi 188

 Writing Testbenches
—  Generating Periodic Data
`timescale 1 ns / 100 ps
module test_moore_detector;
reg x, reset, clock;
wire z;

moore_detector uut ( x, reset, clock, z );

initial begin
clock=1'b0; x=1'b0; reset=1'b1;
end
initial #24 reset=1'b0;
always #5 clock=~clock;
always #7 x=~x;
endmodule
Generating Periodic Data

July 2014 © 2013-2014 Zain Navabi 189

 Writing Testbenches
—  Random Input Data
`timescale 1 ns / 100 ps

module TESTER_test_moore_detector;
reg x, reset, clock;
wire z;
moore_detector uut( x, reset, clock, z );
initial begin
clock=1'b0; x=1'b0; reset=1'b1;
#24 reset=1'b0;
end
initial #165 $finish;
always #5 clock=~clock;
always #7 x=$random;
endmodule
Random Data Generation

July 2014 © 2013-2014 Zain Navabi 190

 Writing Testbenches
—  Timed Data
`timescale 1ns/100ps
module test_moore_detector;
reg x, reset, clock;
wire z;
moore_detector uut( x, reset, clock, z );
initial begin
clock=1'b0; x=1'b0; reset=1'b1;
#24 reset=1'b0;
end
always #5 clock=~clock;
initial begin
#7 x=1; #5 x=0; #18 x=1;
#21 x=0; #11 x=1; #13 x=0;
#33 $stop;
end
endmodule
Timed Test Data Generation

July 2014 © 2013-2014 Zain Navabi 191

 Summary
—  Periodic data
—  Random data
—  Timed data
—  Summary

July 2014 © 2013-2014 Zain Navabi 192

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 16 :
RTL Methodology

July 2014 © 2013-2014 Zain Navabi 193

 RTL Methodology
—  Transistors to processing elements
—  RTL design partitioning
—  Example: serial adder
—  Summary

July 2014 © 2013-2014 Zain Navabi 194

 Transistors Level Design

July 2014 © 2013-2014 Zain Navabi 195

 Gate Level Design

July 2014 © 2013-2014 Zain Navabi 196

 RT Level Design

July 2014 © 2013-2014 Zain Navabi 197

 System Level Design
Connecting CPU’s, memories,
etc. together via channel
interconnections

July 2014 © 2013-2014 Zain Navabi 198

 Datapath And Controller

•  Any element that passes, holds or processes data is a

datapath element
•  Controller is the thinking part of your machine
•  You should decide how to wire datapath elements
•  When designing datapath, don’t be concern about
how control signals are Issued

July 2014 © 2013-2014 Zain Navabi 199

 RTL Datapath Example

July 2014 © 2013-2014 Zain Navabi 200

 RTL Controller Example

Signals that go to or
Come from datapath

July 2014 © 2013-2014 Zain Navabi 201

 Example: Serial Adder
After “start” signal is issued, 8 pairs of serial bits on ain and bin are added and
an 8-bit result is generated.

July 2014 © 2013-2014 Zain Navabi 202

 Design Partitioning

July 2014 © 2013-2014 Zain Navabi 203

 Datapath Design

July 2014 © 2013-2014 Zain Navabi 204

 Controller Design

July 2014 © 2013-2014 Zain Navabi 205

Wiring Of Datapath And Controller

July 2014 © 2013-2014 Zain Navabi 206

 Summary

—  Transistorsto processing elements

—  Design abstraction levels
—  Datapath/controller partitioning
—  Example: serial adder
—  Summary

July 2014 © 2013-2014 Zain Navabi 207

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 17:
RTL Timing

July 2014 © 2013-2014 Zain Navabi 208

 RTL Timing

July 2014 © 2013-2014 Zain Navabi 209

 State Machine Timing

July 2014 © 2013-2014 Zain Navabi 210

 Huffman Model of a Sequential Circuit

—  This much of time allows the combination of PS and PI to

propagate and reach to NS and PO output.
—  Primary outputs producing their values right after the clock ticks
and remain in that way for some time after the next clock tick.

July 2014 © 2013-2014 Zain Navabi 211

 Datapath/Controller Timing

July 2014 © 2013-2014 Zain Navabi 212

 Datapath/Controller Timing

Worst case delay => Clocking

speed

July 2014 © 2013-2014 Zain Navabi 213

 Datapath Timing

—  For finding the clock frequency we should

consider the worst case delay(bottleneck)
of the datapath
—  If we have ALU in datapath, we should
take the delay of ALU operation with the
most delay, as ALU delay
—  Selection of each bus has also its own
delay
—  Each register has setup time delay

July 2014 © 2013-2014 Zain Navabi 214

 Datapath Timing

ttotal = tbus1 + talu-max + tbus2 + tadder+ tbus3 + tsetup

July 2014 © 2013-2014 Zain Navabi 215

 Summary

July 2014 © 2013-2014 Zain Navabi 216

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 18:
RTL Processing Element Design

July 2014 © 2013-2014 Zain Navabi 217

 RTL Processing Element Design

July 2014 © 2013-2014 Zain Navabi 218

 Unsigned Integer Divider
Emphasis is
on a simple
algorithm,
and not very
efficient.

•  Dividing A by B by subtracting B from A until

the remainder is less than B
•  The number of times that subtraction
successfully happens is the quotient
•  The value that is left behind is the remainder
July 2014 © 2013-2014 Zain Navabi 219
 Unsigned Integer Divider

—  The circuit has a 16-bit input bus for A, an 8-bit input bus
for B and two 8-bit buses for remainder and quotient
—  After a complete pulse happens on go, the circuit reads the
A and B operands and division begins
—  After division is completed, circuit places R and Q on the
corresponding buses and issues a one-clock duration pulse
on ready

July 2014 © 2013-2014 Zain Navabi 220

 Unsigned Integer Divider Datapath

July 2014 © 2013-2014 Zain Navabi 221

 Unsigned Integer Divider Controller

July 2014 © 2013-2014 Zain Navabi 222

 Unsigned Integer Divider
Verilog Code of Controller
WHEN output => ready <= '1';ns <= waitOnGo;
WHEN OTHERS =>ns <= waitOnGo;
END CASE;
END PROCESS;

PROCESS(clk)BEGIN
IF((clk='1' AND clk'EVENT))THEN
IF (rst )
ps <= “00”;
ELSE
ps <= ns;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

2
1
July 2014 © 2013-2014 Zain Navabi 223
 Unsigned Integer Divider
Verilog Code of Controller

July 2014 © 2013-2014 Zain Navabi 224

 Unsigned Integer Divider
Verilog Code of Datapath

COMPONENT comparator PORT

( a, b:IN bit_vector(15 DOWNTO 0);
aLtB: OUT BIT);
END COMPONENT;

COMPONENT reg16 PORT( clk, load : IN bit;

regIn: IN bit_vector( 15 DOWNTO 0);
regOut : OUT bit_vector( 15 DOWNTO 0);
END COMPONENT;

COMPONENT reg8 PORT( clk, load : IN bit;

regIn: IN bit_vector( 7 DOWNTO 0);
regOut : OUT bit_vector( 7 DOWNTO 0);
END COMPONENT;

COMPONENT upCounter PORT( clk, rst, inc:IN BIT ;

cntOut : OUT bit_vector( 7 DOWNTO 0);
END COMPONENT;
2 1

July 2014 © 2013-2014 Zain Navabi 225

 Complete Design

July 2014 © 2013-2014 Zain Navabi 226

 Testbench

July 2014 © 2013-2014 Zain Navabi 227

 Summary

July 2014 © 2013-2014 Zain Navabi 228

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 19:
Handshaking

July 2014 © 2013-2014 Zain Navabi 229

 Handshaking

—  Handshaking definition

—  Types of handshaking
◦  Handshaking between two systems
◦  Handshaking for accessing a shared bus
◦  Memory handshaking
◦  DMA mode or burst mode
—  Handshaking with timing details

July 2014 © 2013-2014 Zain Navabi 230

 Why Handshaking?

—  Two systems wants to communicate data

and they don’t necessarily have the same
timing
—  The systems have to send some signals
before the actual data is transmitted
—  Handshaking implementation is a part of
the control of the system

July 2014 © 2013-2014 Zain Navabi 231

 Between two RTLs Handshaking

—  Two systems wants to communicate

data and they don’t necessarily have the
same timing
—  The systems have to send some signals
before the actual data is transmitted
—  Handshaking implementation is a part
of the control of the system

July 2014 © 2013-2014 Zain Navabi 232

 Types of Handshaking

—  Handshaking between two systems

—  Handshaking for accessing a shared bus
—  Memory handshaking
—  DMA mode or burst mode

July 2014 © 2013-2014 Zain Navabi 233

 Handshaking Type One:
Handshaking Between Two Systems

•  Each system has its own clocking

•  They have to have certain signals to talk
July 2014 © 2013-2014 Zain Navabi 234
 Handshaking Type One:
Handshaking Between Two Systems

—  Fully responsive handshaking

July 2014 © 2013-2014 Zain Navabi 235

 Handshaking Type One:
Handshaking Between Two Systems

July 2014 © 2013-2014 Zain Navabi 236

 Handshaking Type One:
Handshaking Between Two Systems

July 2014 © 2013-2014 Zain Navabi 237

Handshaking Type Two:
Handshaking for accessing a shared bus

•  Using an arbiter to assure that none of the systems will

simultaneously access the shared bus
•  Each system has to have its own request and grant signals

July 2014 © 2013-2014 Zain Navabi 238

 Handshaking Type Two:
Handshaking for accessing a shared bus

July 2014 © 2013-2014 Zain Navabi 239

 Two level handshaking

—  Assume that system A wants to send

some data to B through a shared bus
—  At first A should talk to the arbiter and
catches the bus by issuing a request .
—  Once it puts the data on bus it informs
system B by issuing ready
—  After data is picked up by B, A removes
its request.

July 2014 © 2013-2014 Zain Navabi 240

 Two level handshaking

July 2014 © 2013-2014 Zain Navabi 241

 Handshaking Type Three:
memory handshaking

July 2014 © 2013-2014 Zain Navabi 242

 Combining Type Two and Three of
Handshaking
—  We can combine type two and three of
handshaking
—  At first A should deal with arbiter and
gets the permission of using the bus
—  Then it should send signals to the
memory and waits for memready

July 2014 © 2013-2014 Zain Navabi 243

 Handshaking Type Four:
DMA Mode Or Burst Mode

—  Burst writing or DMA writing or block writing

July 2014 © 2013-2014 Zain Navabi 244

 Summary

—  Handshaking definition

—  Types of handshaking
◦  Handshaking between two systems
◦  Handshaking for accessing a shared bus
◦  Memory handshaking
◦  DMA mode or burst mode
—  Handshaking with timing details
—  Summary

July 2014 © 2013-2014 Zain Navabi 245

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 20:
Inter RTL Communications

July 2014 © 2013-2014 Zain Navabi 246

 Inter RTL Communications

July 2014 © 2013-2014 Zain Navabi 247

 Memory Interface: Design Example

DataBus32 Data8
32 8
ReadData32 readData8

addrBus16 Interface addr18 Memory

16 18
memResdy32 memReady8

grant request
July 2014 © 2013-2014 Zain Navabi 248
 Memory Interface: Datapath&Controller Partitioning

July 2014 © 2013-2014 Zain Navabi 249

 Memory Interface: State Machine

memReady32
memReady8
readData32

readData8
LdAddr

Request

LddEn
Grant

incC2
rstC2
coc2

readData32 = 0
Combinational grant = 0

Part
Waiting GetData GetBus
readData32 = 1
no
Register

LdAddr = 1 request = 1
control rstC2 = 1
signals

memReady8 = 0 t=1 readData32=1

gran

clk rst readMem oneByte deliverData

memReady8=1 coc2=1
LdEn=1
readData8=1 memReady32=1
request=1
request=1
Incc2=1

coc2=0

readData32=0

July 2014 © 2013-2014 Zain Navabi 250

 Memory Interface: Datapath Verilog Code

3
2
1
July 2014 © 2013-2014 Zain Navabi 251
 Memory Interface: Datapath Verilog Code

3
2

July 2014 © 2013-2014 Zain Navabi 252

 Memory Interface: Datapath Verilog Code

July 2014 © 2013-2014 Zain Navabi 253

 Memory Interface: Controller Verilog Code

3
2 1

July 2014 © 2013-2014 Zain Navabi 254

 Memory Interface: Controller Verilog Code

3
2

July 2014 © 2013-2014 Zain Navabi 255

 Memory Interface: Controller Verilog Code

July 2014 © 2013-2014 Zain Navabi 256

 Memory Interface: Complete System Verilog
Code

July 2014 © 2013-2014 Zain Navabi 257

 Inter RTL Communications

July 2014 © 2013-2014 Zain Navabi 258

Lecture Series:
Basics of Digital Design at RT Level with Verilog

Z. Navabi, University of Tehran

Basics of Digital Design at RT

Level with Verilog

Lecture 21:
Complete RTL: Processing Elements
and Communications
July 2014 © 2013-2014 Zain Navabi 259
RTL Processing Elements and Communications

July 2014 © 2013-2014 Zain Navabi 260

Bus Based Design

July 2014 © 2013-2014 Zain Navabi 261

Exponentiation Module: Design Example

July 2014 © 2013-2014 Zain Navabi 262

 Exponentiation Module

ResultIntegerPart
ResultFractionPart
done

July 2014 © 2013-2014 Zain Navabi 263

 Exponential Function Algorithm
∞
𝑘
𝑥
e𝑥 = $
𝑘!
𝑘 =0
e = 1;
a = 1;
for( i = 1; i < n; i++ ) {
a = a × x × ( 1 / i );
e = e + a;
}
July 2014 © 2013-2014 Zain Navabi 264
 Datapath / Controller
Co (to controller) ROM

counter

presetc
cntc
i Selx
Seli
16

16
x
Mult
16
loadx
x
16
16

16

Adder

16 18

a e

presete 18
preseta
loade
loada
16

July 2014 © 2013-2014 Zain Navabi 265

 Datapath
Co (to controller) ROM

counter

presetc
cntc
i Selx
Seli
16

16
x
Mult
16
loadx
x
16
16

16

Adder

16 18

a e

presete 18
preseta
loade
loada
July 2014 © 2013-2014 Zain Navabi 16 266
 Controller

July 2014 © 2013-2014 Zain Navabi 267

Exponentiation Module :
Datapath Verilog Code

3
2 1
July 2014 © 2013-2014 Zain Navabi 268
 Exponentiation Module
Datapath Verilog Code

4
2
July 2014 © 2013-2014 Zain Navabi 269
 Exponentiation Module
Datapath Verilog Code

3
July 2014 © 2013-2014 Zain Navabi 270
 Exponentiation Module :
Combinational Table Verilog Code

1
July 2014 © 2013-2014 Zain Navabi 271
 Exponentiation Module :
Controller Verilog Code

3
2 1

July 2014 © 2013-2014 Zain Navabi 272

 Exponentiation Module :
Controller Verilog Code

3
2

July 2014 © 2013-2014 Zain Navabi 273

 Exponentiation Module :
Controller Verilog Code

July 2014 © 2013-2014 Zain Navabi 274

 Exponentiation Module :
Complete System Verilog Code

July 2014 © 2013-2014 Zain Navabi 275

 Input Wrapper:
Datapath & Controller Partitioning

July 2014 © 2013-2014 Zain Navabi 276

Input Wrapper:
State Machine
rst = 1 InReady = 0

InReady = 1
rst = 0 INPUT_ACCEPT PUT_DATA
RESET WAIT_ON_INREADY
InAccept = 1
LoadInput = 1 shiftEn = 1

Count Done && !Count Done &&

!Count Done &&
Done Done
!Done

START
WAIT_ON_DONE
start = 1
counterEn = 1

July 2014 © 2013-2014 Zain Navabi 277

Input Wrapper :
Datapath Verilog Code

1
July 2014 © 2013-2014 Zain Navabi 278
 Input Wrapper :
Controller Verilog Code

3
2 1

July 2014 © 2013-2014 Zain Navabi 279

 Input Wrapper :
Controller Verilog Code

3
2

July 2014 © 2013-2014 Zain Navabi 280

 Input Wrapper :
Controller Verilog Code

July 2014 © 2013-2014 Zain Navabi 281

 Input Wrapper :
Complete Verilog Code

July 2014 © 2013-2014 Zain Navabi 282

 Output Wrapper:
Datapath & Controller Partitioning

July 2014 © 2013-2014 Zain Navabi 283

Output Wrapper:
State Machine

rst = 1 done = 0 grant = 0

done = 1
rst = 0 GET_DATA countDone = 1 WAIT_ON_GRANT
RESET WAIT_ON_DONE
countDone = 0 loadData = 1
counterEn = 1 req = 1

outAccepted = 1

grant = 1
outAccepted = 0

WAIT_ON_OUTACCEPT

outReady = 1

July 2014 © 2013-2014 Zain Navabi 284

Output Wrapper :
Datapath Verilog Code

2 1
July 2014 © 2013-2014 Zain Navabi 285
 Output Wrapper :
Datapath Verilog Code

July 2014 © 2013-2014 Zain Navabi 286

 Output Wrapper :
Controller Verilog Code

3
2 1

July 2014 © 2013-2014 Zain Navabi 287

 Output Wrapper :
Controller Verilog Code

3
2

July 2014 © 2013-2014 Zain Navabi 288

 Output Wrapper :
Controller Verilog Code

July 2014 © 2013-2014 Zain Navabi 289

 Output Wrapper :
Complete Verilog Code

July 2014 © 2013-2014 Zain Navabi 290

 Complete System

July 2014 © 2013-2014 Zain Navabi 291

Complete System

July 2014 © 2013-2014 Zain Navabi 292

 Summary

July 2014 © 2013-2014 Zain Navabi 293

 Series Summary

A complete logic to
RTL course using
HDLs.

July 2014 © 2013-2014 Zain Navabi 294