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Answer 1:: Computer Science and Engineering Department Computer Organisation and Architecture (SE-204)

This document contains a tutorial sheet submitted by Aseem Sangalay to Dr. Pawan Singh Mehra for the course Computer Organisation and Architecture. It discusses different addressing modes used in computer instructions, including implied, immediate, register, register indirect, direct, indirect, PC relative, indexed, auto-increment, auto-decrement, and base address register addressing modes. It also provides examples of three address, two address, one address, and zero address instructions and their operation codes, destination addresses, source addresses, and modes.

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Hariom Sharma
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55 views4 pages

Answer 1:: Computer Science and Engineering Department Computer Organisation and Architecture (SE-204)

This document contains a tutorial sheet submitted by Aseem Sangalay to Dr. Pawan Singh Mehra for the course Computer Organisation and Architecture. It discusses different addressing modes used in computer instructions, including implied, immediate, register, register indirect, direct, indirect, PC relative, indexed, auto-increment, auto-decrement, and base address register addressing modes. It also provides examples of three address, two address, one address, and zero address instructions and their operation codes, destination addresses, source addresses, and modes.

Uploaded by

Hariom Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Delhi Technological University

Computer Science and Engineering Department


Computer Organisation and Architecture (SE-204)
Tutorial Sheet-2

Submitted To: Dr. Pawan Singh Mehra


Submitted By: Aseem Sangalay 2K19/SE/021

Answer 1:

EXPRESSION —> X = ( A + B * C ) / ( D - E / F )

a) Three address instructions

i) M = Any memory location

OPCODE DESTINATION SOURCE SOURCE MODE


ADDRESS ADDRESS ADDRESS

MUL R1 B C R1 <— M[B] * M[C]

ADD R1 R1 A R1 <— R1 + M[A]


DIV R2 E F R1 <— M[E] / M[F]
SUB R2 D R2 R2 <— M[D] - R2
DIV X R1 R2 M[X] <— R1 / R2

b) Two address instructions

i) M = Any memory location


OPCODE DESTINATION SOURCE ADDRESS MODE
ADDRESS

MOV R1 B R1 <— M[B]


MUL R1 C R1 <— R1 * M[C]
ADD R1 A R1 <— R1 + M[A]
MOV R2 E R2 <— M[E]
DIV R2 F R2 <— R2 / M[F]
SUB R2 D R2 <— M[D] - R2
DIV R1 R2 R1 = R1 / R2
MOV X R1 M[X] <— R1

c) One address instructions

i) AC = Accumulator
ii) M = Any memory location

OPCODE OPERAND / ADDRESS OF MODE


OPERAND

LOAD B AC <— M[B]


MUL C AC <— AC * M[C]
ADD A AC <— AC + M[A]
STORE T M[T] <— AC
LOAD E AC <— M[E]
DIV F AC <— AC / M[F]
SUB D AC <— M[D] - AC
DIV T AC <— M[T] / AC
STORE X M[X] <— AC

d) Zero address instructions


i) Reduced Polish Notation — A B C * + D E F / - /
ii) TOP = Top of stack

OPCODE OPERAND MODE

PUSH A TOP <— A


PUSH B TOP <— B
PUSH C TOP <— C
MUL TOP <— B * C

ADD TOP <— A + ( B * C )

PUSH D TOP <— D


PUSH E TOP <— E
PUSH F TOP <— F
DIV TOP <— E / F

SUB TOP <— D - ( E / F )

DIV TOP <— ( A + ( B * C ) ) / ( D - ( E /


F))
POP X M[X] <— TOP

Answer 2:

a) Implied addressing mode - used to reset Carry flag to 0

b) Immediate addressing mode - moves data in AL Register MOV AL, 35H


c) Register addressing mode - MOV AX,CX (move the contents of CX register to AX
Register)
d) Register Indirect addressing mode - MOV AX, [BX] (move the contents of memory
locations addressed by the register BX to the register AX)
e) Direct addressing mode - add the contents of offset address to AL.
f) Indirect addressing mode - address specifies address of the operand not of operand itself.
g) PC relative addressing mode - implements intra segment transfer of control, EA= PC +
Address field value PC= PC + Relative value.
h) Indexed addressing mode - MOV AX, [SI +05] The operand’s offset is the sum of the
content of an index register SI or DI and an 8 bit or 16 bit displacement.
i) Auto-Increment addressing mode - After accessing the operand, the content of the register is
automatically incremented by step size ‘d’.
j) Auto-Decrement addressing mode - First, the content of the register is decremented by step
size ‘d’. After decrementing, the operand is read.
k) Base Address Register addressing mode - ADD AX, [BX+SI]

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