2/26/2020 JeyaTech: Pseudo Random Sequence Generator in Verilog
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Friday, May 18, 2012 About Me
Jeya
Pseudo Random Sequence Generator in Verilog Colombo, Sri
Lanka
Knowledge
Pseudo Random Sequence is widely used in spread spectrum communication, to spread and de- Sharing!!
spread the information sequence. The following diagram shows a PN sequence generator which has 3 View my complete profile
memory elements, leads to processing gain 7 (2^3 - 1). According to the diagram, if the initial state
is all zero, then the sequence will also be all zeros which is not usable.
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module PNSeqGen( OpenCV (1)
input clk, reset, Prolog (1)
output s3 Python (1)
);
reg s1, s2, s3;
wire s0; Popular Posts
// MODULO 2 ADDITION 4 Bit Ripple Carry Adder in
assign s0 = s1 ^ s3; Verilog
// STATE MACHINE
always @ (posedge clk or reset) begin 4 Bit Carry Look Ahead Adder
// INITIAL STATE SHOULDN'T BE 000 => 100 in Verilog
if(reset) begin
4 Bit Priority
s1 <= 1; Encoder in
s2 <= 0; Verilog
s3 <= 0;
end else begin
s1 <= s0; Zoom Images :
s2 <= s1; Nearest
s3 <= s2; Neighbour &
Bilinear
end
Interpolation
end
endmodule Pseudo Random Sequence
Generator in Verilog
Test Bench
tjeyamy.blogspot.com/2012/05/pseudo-random-sequence-generator-in.html 1/3
2/26/2020 JeyaTech: Pseudo Random Sequence Generator in Verilog
`timescale 1ns / 1ps
module Test_PNSeqGen;
// Inputs
reg clk;
reg reset; Region Growing
// Outputs
wire s3;
// Instantiate the Unit Under Test (UUT)
PNSeqGen uut (
Minimum Priority Queue
.clk(clk), Implemented Using Min-Heap
.reset(reset), in C++
.s3(s3)
); Path Finding in Prolog
initial begin
// Initialize Inputs Graph Cut
Segmentation
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
Binary Huffman Code in C++
// Add stimulus here
#10 reset = 1;
#10 reset = 0;
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#200 $finish;
end ► 2013 (3)
always begin ▼ 2012 (10)
#5 clk = ~clk; ▼ May (2)
end Pseudo Random
// PRINT SEQUENCE Sequence Generator
always @ (posedge clk) $write("%b",s3); in Verilog
endmodule 4 Bit Priority Encoder in
Verilog
Output
► February (4)
001110100111010011101 ► January (4)
► 2011 (8)
Posted by Jeya at 1:09 PM ► 2010 (21)
Labels: Communication, Electronics, Verilog
Statistics
6 comments:
Anonymous June 6, 2012 at 12:14 PM
Very helpful. Thank you very much.
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Anonymous May 11, 2016 at 10:45 AM
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Thank you
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Anonymous October 30, 2019 at 12:36 PM Security
9 hours ago
Can you make a verilog code for a sequence generator given one input X and one output Y and output
should be 1, 0, 0, 1, 0, 1? HowStuffWorks Daily
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2/26/2020 JeyaTech: Pseudo Random Sequence Generator in Verilog
Unknown November 23, 2019 at 6:34 PM The Most Embarrassing
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Can u make a verilog code for the same?? Science
7 years ago
Reply
Vaibhav February 12, 2020 at 12:33 AM
can you write code for to genrate pn sequence from 8 bit input
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