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Addressing Modes Part I – Working with AVR's Load-Store RISC Architecure

READING
The AVR Microcontroller and Embedded Systems using Assembly and C)
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Chapter 2: AVR Architecture and Assembly Language Programming

Section 2.3: Using Instructions with the Data Memory

Chapter 6: AVR Advanced Assembly Language Programming

Section 6.2: Register and Direct Addressing Modes

TABLE OF CONTENTS
Load-Store Instructions and the ATmega328P Memory Model ...................................................................................................................................................... 3
Load-Store Instructions and Addressing Modes ............................................................................................................................................................................. 4
Immediate ..................................................................................................................................................................................................................................... 5
Direct ............................................................................................................................................................................................................................................ 6
Register-register Instructions......................................................................................................................................................................................................... 7
Register Direct ............................................................................................................................................................................................................................... 8
Load-Store Program Example ........................................................................................................................................................................................................ 9
Special Topic – Harvard versus Princeton Architecture ................................................................................................................................................................ 10
Appendix A – ATmega328P Instruction Set .................................................................................................................................................................................. 11

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 LOAD-STORE INSTRUCTIONS AND THE ATMEGA328P MEMORY MODEL
When selecting an addressing mode you should ask yourself where is the operand (data) located within the memory model of
the AVR processor and when do I know its address (assembly time or at run time) 1.

FLASH Program
Memory
16K x 16 (32 K bytes)

byte 1 0
0x0000

SRAM Data
Memory SRAM I/O
2 K bytes Address Address
16-bit 0x08FF
Application Word 2048 x 8 SRAM
Flash Address
Section (little- EEPROM Data
endian) Memory
0x0100 1 K byte
0x00FF

160 Ext I/O Reg.

0x0060
0x005F 0x003F
64 I/O Registers
Boot Flash Section
256a2048 words 0x0020 0x0000
0x001F
32 Registers
0x3FFF 0x0000

1
http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf 8-bit AVR Instruction Set

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 LOAD-STORE INSTRUCTIONS AND ADDRESSING MODES
When loading and storing data we have several ways to “address” the data.

The AVR microcontroller supports addressing modes for access to the Program memory (Flash) and Data memory (SRAM,
Register file, I/O Memory, and Extended I/O Memory).

Load-store Instructions

Address Space

Addressing Mode Flash Program SRAM Data I/O

Immediate ldi

Direct lds, sts in, out

Indirect lpm, spm (1) ld, st (2)

Indirect with Displacement ldd, std (3)

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 IMMEDIATE

Data is encoded with the instruction. Operand is therefore located in Flash Program Memory. This is why technically our
memory model is a Modified Harvard.

ldi r16, 0x23 // where ldi = 1110, Rd = 00002, and constant K = 001000112

Notice that only four bits (dddd) are set aside for defining destination register Rd. This limits us to 2 4 = 16 registers. The
designers of the AVR processor chose registers 16 to 31 to be these registers (i.e., 16 ≤ Rd ≤ 31).

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 DIRECT
lds r16, A
sts A, r16
Within the AVR family there are two (2) possible lds/sts instructions. A specific family member will have only one lds/sts combination. The ATmega328P
lds/sts instruction is illustrated here with the exception that 5 bits (not 4) encode Rr/Rd. This means all 32 registers are available to the lds/sts instruction.

21 20

in r16, PINC
out PORTD, r16

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 REGISTER-REGISTER INSTRUCTIONS

Data Transfer

 Register-register move byte (mov)or word (movw)

Arithmetic and Logic (ALU)

 Two’s complement negate (neg), Arithmetic add (add, adc, adiw), subtract (sub, subi, sbc,
sbci), and multiply (mul, muls, mulsu, fmul, fmuls, fmulsu)
 Logical not (com), and (and, andi, cbr, tst), or (or, ori, sbr), exclusive or (eor)
 Clear (clr), set (ser), increment (inc), decrement (dec)

Bit and Bit-Test

 Register logical shift left (lsl) or right(lsr); arithmetic shift right (asr); and rotate left or right (rol, ror)
 Register swap nibble (swap)
 Register bit load (bld) or store (bst) from/to T flag in the Status Register SREG
 I/O Register Clear (cbi) or set (sbi) a bit
 Clear (clFlag) or set (seFlag) a Flag bit in the Status Register SREG by name (I, T, H, S, V, N, Z, C) or bit
(bclr, bset).

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 REGISTER DIRECT
In the following figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To
generalize, the abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space.

com r16

add r16, r17

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 LOAD-STORE PROGRAM EXAMPLE
Write an Assembly program to add two 8-bit numbers.
C=A+B
lds r16, A ; 1. Load variables
lds r17, B
add r16, r17 ; 2. Do something
sts C, r16 ; 3. Store answer

 Identify the operation, source operand, destination operand in the first Data Transfer
instruction.

 Identify the source/destination operand in the Arithmetic and Logic (ALU) instruction.

 What addressing mode is used by the source operand, in the first instruction?

 Show contents of Flash Program Memory (mnemonics)

 Show contents of SRAM Data Memory, assuming variables are stored in sequential memory
locations starting at address 010016.

 Modify the program to leave register r16 unchanged by making a copy (use r15).

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 SPECIAL TOPIC – HARVARD VERSUS PRINCETON ARCHITECTURE
Princeton or Von Neumann Memory Model

Program and data share the same memory space. Processors used in all personal computers, like the Pentium, implement a von
Neumann architecture.

Harvard Memory Model

Program and data memory are separated. The AVR processors among others including the Intel 8051 use this memory model. One
advantage of the Harvard architecture for microcontrollers is that program memory can be wider than data memory. This allows the
processor to implement more instructions while still working with 8-bit data. For the AVR processor program memory is 16-bits wide
while data memory is only 8-bits.

You may have already noticed that when you single step your program in the simulator of AVR Studio it is incremented by 1 each time
an instruction is executed. No surprise there right? Wrong. The program memory of the AVR processor can also be accessed at the
byte level. In most cases this apparent paradox is transparent to the operation of your program with one important exception. When
you want to access data stored in program memory, you will be working with byte addresses not words (16-bits). The assembler is
not smart enough to know the difference and so when you ask for an address in program memory it returns its word address. To
convert this word address into a byte address you need to multiply it by 2. Problematically we do this by using the shift left syntax of
C++ to explicitly tell the assembler to multiply the word address by 2. Remember, when you shift left one place you are effectively
multiplying by 2.

With this in mind, we would interpret the following AVR instruction as telling the AVR assembler to convert the word address of label
beehives in program memory to a byte address and then to take the low order of the resulting value and put into the source operand
of the instruction.

ldi ZL,low(beeHives<<1) // load word address of beeHives look-up

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 APPENDIX A – ATMEGA328P INSTRUCTION SET2

2
Source: ATmega328P Data Sheet http://www.atmel.com/dyn/resources/prod_documents/8161S.pdf Chapter 31 Instruction Set Summary
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