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Dma Operation in An 8086 Based System

The document describes how DMA operation works in an 8086-based system. It explains that the DMA controller temporarily takes control of the address, data, and control buses from the microprocessor to directly transfer data between peripherals and memory. This is faster than programmed I/O because the transfer is handled by hardware instead of the microprocessor. It also provides step-by-step details of the sequence followed to perform a disk read operation using DMA.

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388 views3 pages

Dma Operation in An 8086 Based System

The document describes how DMA operation works in an 8086-based system. It explains that the DMA controller temporarily takes control of the address, data, and control buses from the microprocessor to directly transfer data between peripherals and memory. This is faster than programmed I/O because the transfer is handled by hardware instead of the microprocessor. It also provides step-by-step details of the sequence followed to perform a disk read operation using DMA.

Uploaded by

Sowmya P
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DMA OPERATION IN AN 8086 BASED SYSTEM

 DMA controller temporarily borrows the address bus, data bus


and control bus from the microprocessor and transfers the data
bytes directly from the port to a series of memory locations.
 Because the data transfer is totally handled by Hardware, it is
much faster than programmed data transfer.
 Microprocessor and DMA controller time-share the use of
address, data and control buses.
 When the system is first turned on the buses are connected from
microprocessor to system memory and peripherals.
To read a disk file the following sequence of steps are followed:
1. Microprocessor sends series of commands to disk controller
informing it to read the desired block of data from the disk and
main memory address where it is to be stored.
2. When the first byte of the data is ready, disk controller sends a
DMA request (DREQ) signal to the DMA controller.
3. If that channel is unmasked, the DMA controller sends HRQ to the
Microprocessor HOLD input.
4. Microprocessor responds to this input by floating its busses and
sending out an HLDA signal to the DMA controller after the
current bus cycle.
5. When DMA controller receives the HLDA signal it takes the control
of three buses.
6. The DMA controller then outputs on the address bus the memory
address where the byte is to go from disk controller.
7. Next DMA controller sends a DMA acknowledge (DACK) to the
disk controller device to enable it to output the data.
8. Finally DMA controller asserts MEMW and IOR lines on the
control bus, to enable the addressed memory and to output the
data byte from the disk controller on the data bus. The byte of
data will then be written to the addressed memory location.
9. When the data transfer is complete the DMA controller un asserts
its hold-request signal to the processor.
For Write Operation DMA controller asserts MEMR and IOW control
signals. DMA transfers may b e Byte or Blocks.
Types of DMA Transfers:
Block Transfer: DMA controller gives the control of system bus to
the processor only after transferring the entire block.
Cycle Steeling: DMA controller takes one or two bus cycles from
the processor, transfers the data and gives the control back to
the processor.
Transparent DMA: Takes the control of the system bus only
when the processor is not utilizing the system bus.
BUS TIMINING DIAGRAM FOR 8237 DMA CONTROLLER

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