7 COA -Notes 3" Year CSE Dr. Rajender Kumar / CSG 2 5S UNIT-II Zo. a ion and Design: Instruction codes. stored program organization, Basic Computer orgat computer registers and common bus system, computer instructions, timing and control, instruction cycle: Fetch and Decode, Register reference instructions; Memory reference instructions. Input, output and Interrupt: configuration, instructions, Program interrupt, Interrupt cycle, Micro- programmed Control organization, Control Memory, address sequencing, Micro program Example, micro instruction format, Horizontal Vs Vertical micré-programming. design of control Unit, micro program sequencer, Hardwired v/s Micro-Programmed Control Unit. COMPUTER ARCHITECTUR! INSTRUCTION COD: An instruction code is a group of bits that instruct the computer to perform a specific operation. The operation code of an instruction is a group of bits that define operations such as addition, subtraction, shift, complement, etc. An instruction must also include one or more operands, which indicate the registers and/or memory addresses from which data is taken or to which data is deposited. Micro-operations-The instructions are stored in computer memory in the same manner that data is stored. The control unit interprets these instructions and uses the operations code to determine the sequences of micro-operations that must be performed to execute the instruction. An instruction code categorized into two elements as Operation codes (Opcodes) and Address. Opcodes specify the operation for specific instructions. An address determines the registers or the areas that can be used for that operation. Operands are definite elements of computer instruction that show what information is to be operated on. Instruction Format Addressing Mode 4 opcode Address 45 44 4244 0 Tt consists of 12 bits of memory that are required to define the address as the memory includes 4096 words. The 15th bit of the instruction determines the addressing mode (where direct addressing corresponds to 0, indirect addressing corresponds to 1). Therefore, the instruction format includes 12 bits of address and 1 bit for the addressing mode, 3 bits are left for Opcodes.NRG a 8 ¢ Dr.RajenyO 2 2 COA -Notes 3" Year CSE . bender, oe There are three parts of the Instruction Format which are as follows ~ Addressing Modes Instructions that define the address of a definite memory location are known as memory reference instructions, The method in which a target address or effective address is recognized within the instruction is known as addressing mode. ‘The adress field for instretion can be represented in two different ways areas follows — Direet Addressing ~ it uses the address of the operand, Indirect Addressing ~ It facilitates the address as a pointer to the operand, ‘The address of the operand or the target address is called the effective address, Effective Address (EA) ~ 11 defines the address that can be executed as a target address for a branch type instruction or the address that can be used directly to create an operand for a computation type instruction, without creating any changes. Opcodes An Opcode is @ collection of bits that represents the basie operations including add, subtract, ‘multiply, complement, and shift. The total number of operations provided through the computer Getermines the number of bits needed for the opcode. The minimum bits accessible to the Opcode Should be n for 2n operations. These operations are implemented on information that is saved in Processor registers or memory. Address ‘The address is represented as the location where a specific instruction is constructed in the memory. The address bits of an instruction code is used as an operand and not as an address. In such methods, the instruction has an immediate operand, If the second part has an address, the instruction is referred to have a direct address. There is another possibility in the second part including the address of the operand. This is referred to as an indirect address. In the instruction code, one bit can signify if the direct or indirect address is executed. STORED PROGRAM ORGANIZATION 7 The simplest way to organize a computer is to have one processor register and an instruction code format with two parts. The first part specifies the operation to be performed and the second 2 a ECOA -Notes 3 Year CSE Dr. Rajender Kumar specifies an address: The memory address tells the control where to find an operand in memory. ‘This operand is reed from memory and used as the data to be operated on together with the data stored in the processor register, Figure below depicts this type of organization. Instructions are stored in one section of memory and data in another. For a memory unit with 4096 words we need 12 bits to specify an address since 212 = 4096. If we store each instruction code in one 16-bit memory word, we have available four bits for the operation code (abbreviated opcode) to specify one out of 16 possible operations,‘ and 12 bits to specify the address of an operand. The control reads a 16-bit instruction from the program portion of memory. It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion of memory. It then executes the operation specified by the operation code. Figure Stored program organization. Memory 4096 % 16 SSS 15 12 2 ‘Opeode ‘Address Instructions (program) Instruction format 1s Operands Binary operand (data) L———~___} Processor register (accumulator or AC) Computers that have a single-processor register usually assign to it the name accumulator and label it AC. The operation is performed with the memory operand and the content of AC. If-an operation in an instruction code does not need an operarid from memory, the rest of the bits in the instruction can be used for other purposes. For example, operations such as clear AC, complement AC, and increment AC operate on data stored in the AC register. They do not need an operand from memory, For these types of operations, the second part of the instruction code (bits 0 through 11) is not needed for specifying a memory address and can bbe used to specify other operations for the computer,COA Notes 3" Year CSE Dr. Rajender Kumar specifies an address, The memory address tells the control where to find an operand in memory. This operand is read from memory and used as the data to be operated on together with the data stored in the processor register. Figure below depicts this type of organization. Instructions are stored in one section of memory and data in another. For a memory unit with 4096 words we need 12 bits to specify an address since 212 = 1096, If we store each instruction code in one 16-bit memory word, we have available four bits for the operation code (abbreviated opcode) to specify one out of 16 possible operations, * and 12 bits to specify the address of an operand. ‘The control reads a 16-bit instruction from the program portion of memory. It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion of memory. Itthen executes the operation specified by the operation code. Figure Stored program organization. Memory 4096 % 16 Se 15 ow ° {_ Opcode ‘Address, Instructions (program) Instruction format 15 ° aoe ‘Binary operand (Gata) L————___] ‘Processor register (accumulator oF AC) ‘Computers that have a single-processor register usually assign to it the name accumulator and label it AC. The operation is performed with the memory operand and the content of AC. If.an operation in an instruction code does not need an operavid from memory, the rest of the bits in the instruction can be used for other purposes. For example, operations such as clear AC, complement AC, and increment AC operate on data stored in the AC register. ‘They do not need an operand from memory. For these types of operations, the second part of the instruction code (bits 0 through 11) is not needed for specifying a memory address and can ‘be used to specify other operations forthe computer.ee COA -Notes 3" Year CSE Dr. Rajender COMPUTER REGISTERS AND COMMON BUS SYSTEM Registers are a type of computer memory used to quickly accept, store, and transfer data ‘and instructions that are being used immediately by the CPU, The registers used by the CPU are often termed as Processor registers, A processor register may hold an instruction, a storage address, or any data (such as bit sequence or individual chatacters), ‘The computer needs processor registers for manipulating data and a register for holding a memory address. The register holding the memory location is used to calelate the address of the next instruction afer the exeeution of the curren instruction is completed, Following is the list of some of the most common registers used in a basic computer: Register Symbol] Data register DR 16 Holds memory operand ister [AR 12 Holds address for the memory Accumulator AC 16 Processor register Instruction register | IR 16 Holds instruction code Program counter PC 12 Holds . address. of the instruction Temporary register | TR 16 Holds temporary data Input register Iver | 8 Carries input character _ ourR | 38 Carries output character %COA -Notes 3" Year CSE Dr, Rajender Kumar The folowing image shows the register and memory configuration for a basie compute; Register and Memory Configurat ofa basic computer: I 1” ° | SERS | 0 © : Memo: i 4096 words | 46 bits per word i ‘ e 1 15 o | eA ATR Gay zy o-7 ary SEER) [SRR © The Memory unit has a capacity of 4096 words, and ench word contains 16 bits © The Data Register (DR) contains 16 bits which hold the operand tead from the memory location, @ The Memory Address Register (MAR) contains 12 bits which hold the address for the memory location, © The Program Counter (PC) also contains’ 12 bits which hold the address of the next instruction to be read from memory after the current instruction is executed, © The Accumulator (AC) register isa general purpose processing register. © The instruction read ftom memory is placed in the Instruction register (IR). © The Temporary Register (TR) is used for holding the temporary data during the processing, © The Input Registers (IR) holds the input characters given by the user, © The Output Registers (OR) holds the output after processing the input data COMMON BUS SYSTEM We shall study the common bus system ofa very basic computer in this article, A basic computer has 8 registers, memory unit and a control unit, To avoid excessive wiring, memory and all the register are connected vin a common bus. The specific output that is selected for the bus is determined by $2S1S0. The register whose LD (Load) is enable receives the data from the bus. 5seececceeeee eee ay ¢ COA =Notes 3" Year CSE Dr. Rajender Kyy, Registers can be incremented by setting the INR control input and can be cleared by setting yy. CLR control input. The Accumulator's input must come via the Adder & Logie Circuit. This allows the Accumulator and Data Register to swap data simultaneously. The address of any memory location being accessed must be loaded in the Address Register. Basic Computer Organization & Design 1 Registers COMMON BUS SYSTEM Outputs of the six registers end memory unit are connected to the common bus of 16 lines, The specific output is selected from the binary value of the selection variables $2, $1, $0. The lines from the commén - bus are connected to the inputs of each register and the daainputofthe memory. The particular register whose LD (Load) input is enabledrecelvesthe data from the bus, INPR receives the @ character from an input device and whichis then transferred to AC. OUTR receive the character from AC and delivers itto D —_thomonhis — an output device, Computer Organization Computer ArchitecturesCOA —Notes 3“ Year CSE Dr, Rajender Kumar Connections: Hee magete af all the registers exept the GUTR. (output register) ars connected to the common bus. The ourput selected depends upon te binary value of variables $2, $1 and SO. The lines from Common us are connected fo the inputs of the registers and memory. A register receives the information from the bus when its LD (load) input is activated while in ease of memory the Write Matic aoe when its Read input is activated, Various Registers: “registers DR, AC, IR and TR have 16 bits and 2 registers AR and PC have 12 bits, The INPR and OUTR have § bits each. The INPR receives character ftom input device and delivers it tothe AC while the OUTR receives character ffom AC and transfers it to the output device. § registers Rave 3 contol inputs LD (load) INR (increment) and CLR (clear). These types of registers are similar to a binary counter. Abbreviation Register name OUTR ‘Ouiput register i TR Temporary register TR Tnstruction register INPR Taput register AC Accumulator DR Data register e PC Program counter AR Address register Adder and logic circuit: The adder and logic circuit provides the 16 inputs of AC. This circuit has 3 sets of inputs, One set comes from the outputs of AC which implements register micro operations. The other set comes Som the DR (data register) which are used to perform arithmetic and logic micro operations, The result of these operations is sent to AC while the end around carry is stored in E as shown in iagram. The third set of inputs is fom INPR.UV & Dr. Rajender x, COA -Notes 3° Year CSE wy COMPUTER INSTRUCTIONS i i a particular proces Computer instructions are a set of machine language instructions that & P: processor revieethanh antadeulen A tomer perl tasko on the benign ie iatraation privied An instruction comprises’of groups called fields. These fields include: © The Operation code (Opcode) field which specifies the operation to be performed. © The Address field which contains the location of the operand, i.e., register or memory location, © The Mode field which specifies how the operand will be located. A basic computer has three instruction code formats which are: 1. Memory - reference instruction 2. Register - reference instruction 3, Input-Output instruction Memory reference instruction ws won 1 opcove MEMORY ADDRESS In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the addressing mode 'T, Memory Reference - These instructions refer to memory address as an operand, The other operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and 1-bit addressing mode for direct and indirect addressing. Example IR register contains = 00OIXXXXXXXXXXXX, ie. ADD after fetching and decoding of instruction we find out that it is a memory reference instruction for ADD operation.COA -Notes 3" Year CSE Dr. Rajender Kumar Hence, DR — M[AR] AC — AC +DR, SC —0 Basic Memory-Reference Instructions Operation Symbol Details AND Decoder |Symbolic Description Performing bitwise AND operation | __P2 AC = ACh. M[AR] | ADD [adds together its two operands D | ICoaD Accumulator with the | LDA ontents from memory = STore Accumulator contents in Sn |ipeie Ds | [The Branch Unconditionally (BUN) instruction ean send the instruction | at is determined by the effective \ddress Ds 'C — AR BSA’ pranch and Save retum Address Ds LAR] [The Increment if Zero (SZ) instruction increments the word TSZ _ fscrermined by effective address Pe MIAN) BUN CPC ARF T [AR] — M[AR] +1, = Othen PC — PC +1 4 Adie C a" = 7 REGISTER OFER, ‘The Register-reference instructions are represented by the Opcode 111 with a0 in the leftmost bit (bit 15) of the instruction. A Register-reference instruction specifies an operation on or a test of the AC (Accumulator) register. Register Reference — These instructions perform operations on registers rather than memory addresses. The IR(14'~ 12) is 111 (differentiates it from memory referenice) and IR(15) is 0 (differentiates it from input/output instructions). The rest 12 bits specify register operation.Dr, Rajende COA -Notes 3" Year CSE ender ky, Example seo ne IR register contams = 0111001000000000, ie. CMA after fetch and decode cycle we find ous y itis register reference instruction for complement accumulator, Henee, AC ©. ~AC ize o INPUT/OUTPUT OPERATION Just like the Register Teference instruction, an Input-Output instruction does not need a reference and 8 recognized by the operation code 111 with a I in the leftmost bit of the instruction, The to memory Femaining 12 bits are used to specify the type of the input-output operation or test performed, Inpuv/output —These instructions are for communication between computer and out Savironment. The IR (14 ~ 12) is 111 (differentiates it from memory reference) and IR (15) is 1 (differentian it Gom register reference instructions). The rest 12 bits specify VO operation. Example IR register contains = 1111100000000000, ie. INP after fetch and decode cycle we find out that it is an input/output instruction for inputting character. Hence, INPUT character om per ipheral device, ‘The set of instructions incorporated in16 bit IR register are: J. Arithmene, logical and shift instuetions (and, edd, complement, circulate left, right, ete) 2. To move information to and from memory (store the accumulator, load the accumulator) 3. Program control instructions with status conditions (branch, skip) 4. Input ouput instructions (input character, output character) Note 10COA Notes 3" Year CSE Dr. Rajender Kumar © The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise, the instruction is a memory-reference type, and the bit in position 15 is taken as the addressing mode I. e When the three operation code bits are equal to 111, control unit inspects the bit in position 15, If the bit is 0, the instruction is a register-reference type. Otherwise, the instruction is an input-output type having bit 1 at position 15, TIMING AND CONTROL All sequential cjreuits in the Basic Computer CPU are driven by a master clock, with the exception of the INPR register. At each clock pulse, the control unit sends control signals to control inputs of the bus, the registers, and the ALU. Control unit design-and implementation can be done by two general methods: A hardwired control unit is designed from scratch using traditional digital logic design techniques to produce a minimal, optimized circuit. In other words, the control unit is like an ASIC (application-specific integrated circuit), A micro-programmed control unit is built from some sort of ROM. The desired control signals are simply stored in the ROM, and retrieved in sequence to drive the miero-operations needed by a particular instruction. INSTRUCTION CYCLE The instruction cycle is related to the CPU (Central processing unit), alist of steps that follows hen the computer system starts until the computer system is shut down, The other name of the instruction cycle is the fetch-decode-execute cycle. There are basically four phases in the instruction cycle: fetching an instruction ftom memory, decoding of the fetched instruction, reading of the address from.memory, and the last phase include the instruction execution. The computer processor executes it. In the computer system, all the instructions are executed in the RAM of the computer system, The CPU is responsible for executing the instruction. The CPU system first fetches the data and instruction from the main memory and store in the temporary memory, which is known as registers. This phase is known as the fetch cyele. After fetching an instruction from memory, the 11Dr. Rajender yy, m se ext step taken by the CPU is devoding of fetched instr ‘There are basically five stages of the instruction eycle which are described below: 1. Initiating Cycle {i this phase, the computer system boots up, and the operating system loads in the main memory {reattonly memory) of the central processing unit. 1k immediately begins when the computer system stats 2, Fetching of Instruction ‘The fetching of instruction isthe first phase. The fetch instruction is common for each instruction executes in a cental processing unt. In this phase, the central processing unit sends the PC to MAR and then sends the READ command into a control bus. After sending a read command on the data bus, the memory retuins the instruction, which is stored at that Particular address in the memory, Then, the CPU copies data from the data bus into MBR and then ‘copies the data fom MBR to registers, After allthis, {he pointer is incremented to the next memory location so that the next instruction can be fetched from. memory, 3, Decoding of Instruction ‘The decoding of instruction is the second phase. In this phase, the CPU determines which instruction is fetched from the instruction and what action needs to be performed on the instruction. The opeode for the instruction is also fetched from memory and decodes the related eration which needs to be performed for the related instruction, R tion. This phase is Know a ted “eCOA Notes 3" Year CSE Dr, Rajender Kumar 4. Read of an Effective Address The reading of an effective address is the third phase. This phase deals with the decision of the operation. The operation can be of any type of memory type non-memory type operation, Memory _bstruction can be categorized into two eategoris direct Memory instruction and indirect memory instruction, 5. Executing of Instruction The executing of instruction is the last Phase. In this stage, the instruction is finally executed, The ‘struction is executed, and the result of the instruction is stored in the register. After the Processor, Importance of Instruction Cycle * Ttis important for the processor system for the central Processing unit as the instructions are the basic operations that are performed in the main memory of the central processing unit, * leis set ofsteps that help to understand the flow of instruction, By the instruction end to end the flow of instructions ean be visualized in the computer processor, yele, the * 18s common for all instruction set it needs to properly understand so that all the operations can be performed easily. * By the instruction cycle, the processing time of the program can be easily calculated, which helps to determine the speed of the processor, + _ As the speed of the processor tells how many instructions can be simultaneously executed in the central processing unit, OUTPUT CO) TION qn computer architecture, input-output devices act as an interface between the machine and the user. Tastructions and data stored in the memory must come from some input device, The results are displayed to the user through some output device. The following block diagram shows the input-output configuration fora basic computer, BCOA -Notes an Year" csE ‘ computer Flip Flops registers & tl input - output conriguts Wy ei tion. The input-output terminals send and receive informat 4 will always have eight bits ofan alphanumeric code. shifted into an input register ‘INPR'. ‘OUTR'. The amount of information transferre ‘The information generated through the keyboard is ‘The information for the printer is stored in the output register os : ue Registers INPR and OUTR communicate with a communication interface serially and with th AC in parallel. smitter interface receives information from the keyboard and transmits it to INPR. iver interface receives information from OUTR and sends it to the printer serially. Design of a Basic Computer A basic computer consists of the following hardware components, 1. A memory unit with 4096 words of 16 bits each 2. Registers: AC (Accumulator), DR (Data register), AR (Address register), IR (Instruction register), PC (Program counter), TR (Temporary register), SC (Sequence Counter), INPR (Input register), and OUTR (Output register), 3. Flip-Flops: I, $, E, R, IEN, FGI and FGO 4, Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder 5. A 16-bit common bus 6. Control Logie Gates 7. The Logic and Adder citcuits connected to the input of AC, 14COA -Notes 3 Year CSE Dr. Rajender Kumar PROGRAM INTERRUPT: Program interrupt defines the transfer of program control from a currently running program to another service program as a result of an extemal or internal created request. Control returns to the initial program after the service program is implemented There are three major types of program interrupts that are as follows ~ External Interrupts Extemal interrupts come from input-output (V0) devices, from a timing device, from a circuit monitoring the power supply, or from any other extemal source. The timeout interrupt can result from a program that is in an endless loop and thus exceeded its time allocation. Power failure interrupt can have as its service routine a program that transfers the complete state of the CPU into a non-destructive memory in a few milliseconds before power ceases. Internal Interrupts Internal interrupts arise from illegal or erroneous use of an instruction or data, Internal interrupts are also called traps. These error conditions generally appear as a result of premature termination of the instruction execution. The service program that processes the internal interrupt determines the corrective measure to be taken. The main difference between. intemal and extemal interrupts i$ that the intemal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event. Internal interrupts are synchronous with the program while extemal interrupts are asynchronous. If the program is rerun, the internal interrupts wvill appear in the same place each. time, External interrupts depend on external conditions that are independent of the program being executed at the time, Software Interrupts A software interrupt is i tiated by executing an instruction, A software interrupt is a special call instruction that behaves like an interrupt rather than a subroutine call. Tt can be used by the programmer to initiate an interrupt procedure at any desired point in the program. 15Dr. Rajender COA -Notes 3" Year CSE INTERRUPT CYCLE yele, fetch-decode- * An instruction cyele (sometimes called fetch-and-execute cy’ ‘ hich a com or FDX) is the basic operation eycle of a computer, It is the process by which a computer ecUte cycle i actions the instruction Tetrieves a program instruction from its memory, determines what ; inuously by the central Fequites, and carries out those actions, This cycle is repeated continuously by Ears Processing unit (CPU), from boot up to when the computer is shut down. * Consider the condition tha the interrupts are enabled, In this case, ffan interrupt occurs then ‘he processor halt he execution ofthe current program. Thereby it saves the address of the "rsiniction that has to be exeeuted next and service the occurred interrupt. To process the interupts the processor set the program counter with starting address of the "NTU service routine, This would let the processor fetch the first instruction of interrupt “ence routine and service the occured interrupt. Once the interrupt is serviced the processor ‘esumnes back to the execution of the program it has halted to service the interrupt, It set the Program counter with the address of the next instruction to be executed, If the interupts are disabled then the processor vill simply ignore the occurrence of interrupts. The processor will smoothly execute the currently running program and will check the pending interrupts once the interrupts are enabled Fetch Cycle Execute Cycle Interrupt Cycle z Fetch Nex lig start. ea ut Instruction "fit * Affer the execute cycle is completed, ates is made to determine if an interrupt was enabled (©, so that another process can acess the CPU) {fnor, instruction eyele retums to the fetch cycle ‘so, the interrupt eyele eight perform the following tasks: (simplified...)42 COA ~Notes 3*# Year CSE Dr. Rajender Kumar * move the current value of PC into MBR + Move the PC-save-address into MAR * move the interrupt-routine-adiress into PC * Move the contents of the address in MBR into indicated memory cell * Continue the instruction cycle within the interrupt routine * after the interrupt routine finishes, the PC-save-address is used to-reset the value of PC and rogram execution can continue ‘Figure: Flowchart of interrupt cycle v7Dr. Rajender yy COA -Notes 3" Year CSE Venter iy MICRO-PROC ROL ORGANIZATION: MICRO-PROGRAMMED CONTROL ORGANIZATION: A control unit whose binary control values are saved as words in memory is called a wyieyy, Programmed control unit A controller results in the instiuetions to be implemented by constructing a definite collection of signals at each s stem clock beat, Each of these output signals generates one micro-operation inchading ster transfer, Thus, the sets of control signals are generated definite micto- ‘operations that can be saved in the memory. Each bit that forms the microinstruction is linked t0 one control signal. When the bit is set, the sontrol signal is active, When it is cleared the control signal tums inactive, ‘These - Sromstructions in a sequence can be saved in the intemal ‘eontrol’ memory. The control unit of micro-program controlled computer is a computer inside a computer The following image shows the block diagram of a Mlcro-programmed Control organization, Micro Programmed Control Organization External Input wextaaaress xeAdaress.) Eonar eaarena (Contal Nomony Control Word aol (Rom) (Sequencer) There are the following steps followed by the micro-programmed control are — + Tecan execute any instruction, The CPU should divide it down into a set of sequential operations, TI is set of operations are called microinstruction, The sequential micro- operations need the control signals to execute. + Control signals saved in the ROM are created to execute the instructions on the data direction. These control signals can control the micro-operations concemed with a microinstruction that is to be performed at any time step. + The address of the microinstruction is executed next is generated, + The previous 2 steps are copied until all the microinstructions associated with the instruction in the set are executed, 8Moveaqce ame | a = S COA -Notes 3" Year CSE, Dr. Rajender Kumar. The address that is supported to the control ROM originates from the micro counter register. The micro counter received its inputs from a multi current address Incrementer, iPlexer that chooses the output of an address ROM, a ind an address that is 'd in the next address field of the current microinstruction. Advantages of Micro-programmed Control Unit There are the following advantages of micro-proprammed control are as follows ~ * Itcan more Systematic design of the control unit, + Itis simpler to debug and change. + Itcan retain the underlying structure of the control function + Tt-can make the design of the control unit much simpler. Hence, it is inexpensive and less error-prone. + Itcan orderly and systematic design process. + Ttis used to control functions implemented in software and not hardware * Itis more flexible and used to complex function is carried out e Disadvantages of Micro-programmed Control Unit There are the following disadvantages of micro-programmed conteol areas follows + Adaptability is obtained at more cost, + Itis slower than a hardwired control unit, CONTROL MEMOR’ A control memory is a part of the control unit. Any computer that involves micro-programmed control consists of two memories. They are the main memory and the control memory. Programs are usually stored in the main memory by the users. Whenever the programs change, the data is also modified in the main memory. They consist of machine instructions and data The control memory consists of microprograms that are fixed and cannot be modified frequen: They contain microinstructions that specify the internal control signals required to execute register micro-operations, ‘The machine instructions generate a chain of microinstructions in the control memory. Their function is to generate micro-operations that can fetch instructions from the main memory, 9Dr. Rajender COA -Notes 3" Year CSE x star etch. phase compute the effective aires, ekcoute the operation, an retum control t0 fetch phase y continue the eyele, Here, the control is presumed t be a Read-Only Memory (ROM), where all the contro, information is stored permanently, ROM provides the address of the microinstruction, The other Fegister, that is, the control data register stores the microinstruction that is read from the memory, a processor. consists ofa control word that holds one or more micro-operations for the data processor The next address must be computed once this operation is completed, It is computed in the next address generator, Then, itis sent to the control address register to be read. The next address Senerator is also known as the micro-program sequencer, Based on the inputs to a sequencer, it dltermines the adktress of the next microinstruction, The microinstructions ean be specified in several ways, Misroinstructions are saved in control memory in groups, These groups describe routines, ach SOmputer instruction bas its micro-program routine that can ereate miero-operations, These micto= operations can execute instructions. The hardware consists of controls for the address sequencing of the miroinstuctions ofa similar routine, They also branch the microinstructions, There are the following phases that the control has w instruction - : implementing a computer + When power is tumed on, and address is initially londed into the control address register. (This {s the address ofthe first microinstruction). + The control address register is incremented resulting in sequencing the fetch routine, * After the fetch routine, the instruction is present inthe IR of the ‘computer, Next, the control memory retrieves the effective address of the operand from the routine, * Thus, the mapping process appears ffom the instruction bits to « control mnemory address. 11 depends on the Opcodes of instruction the microinstructions of the Processor registers are generated, program routine stored. + The instruction code bits are changed into the address where the ro tine is placed and is known as the mappit S Process. A mapping process transforms the microinstruction into a control memory address, + Next, subroutines are called and processes are retuned, 20COA -Notes 3" Year CSE Dr. Rajender Kumar + Aterthe completion ofthe routine, the control addess register is incremented to sequence the instruction is implemented. Selection of Address for Control Memory Instruction Code Mapping Logle Multiplexers [Subroutine Register (SBR) Control Address Register sy (CAR) Incrementer Micro operations The diagram shows the block diagram of a control memory and its associated hardware to support in choosing the next microinstruction, The microinstruction present in the control memory has a set of bits that facilitate to start off the micro-operations in registers ‘There are four different directions are showed in the figure from where the control address register recovers its address, The CAR is incremented by the incrementer and selects the next instruction, In multiple fields of microinstruction, the branching address can be determined to result in branching. Tt can specify the condition of the status bits of microinstruction, conditional branching can be applied. A mapping logic circuit can share an external address, A special register can save the retum address so that when the mioro-program needs to return from the subroutine, it can need the value fiom the unique register. a4 © Dr Rajender COA Notes 3’ Year CSE & MICRO INSTRUCTION FORMAT. this i r ‘A microinstruction format includes 20 bits in total, They are divided into four elements ag displayed in the figure. Microinstruction Code Format ‘ a a 2 2 7 iam L_s a BR AD) | FI, F2, F3 are the micro-operation fields, They determine micro-operations for the computer. CD is the condition for branching. They choose the status bit conditions. BR is the branch field, It determines the type of branch. AD is the address field. It includes the address field whose length is 7 bits. The two widely used formats employed for micro-instructions are vertical and horizontal, In horizontal micro-instruction every bit of micro-instruction nifies a control signal that directly controls a single bus line or occasionally a gate in the machine, Though the length of such a ‘micro-instruction can be hundreds of bits. A typical horizontal micro-instruction with its related fields is demonstrated in Figure below. Inelry dual control Individual contro! | sigral for imeral signal for system | CPU control Amicroinstuction Bus control | \ Jump conditions | (unconditional. cro, | overflow, indirect) Microinstruction branch address (a) Horizontal Micro-instruction 2COA ~Notes 3" Year CSE Dr. Rajender Kumar Ina vertical micro-instrction several similar control signals can be e instruction bits. For example, nneodled in a few micro for 16 ALU operations that may need 16 individual contiol bits in horizontal micro-instruction only 4 encoded bits are Tequired in vertical micro-instruction. In the same way in vertical micro-instruetion only 3 bits registers. Though these encoded bits need! to he individual control signals, ‘we required to select onc of cight Passed from the respective decoders to get the Individhead ‘control signa Indtviduat ‘control stigmas « Microinstruction branch address oo ‘Phen (b) Vertical Micro-instructions DESIGN OF CONTROL UNIT Control Unit is the part of the computer's central processing unit (CPU. which dieets the operation ofthe processor It was included as part ofthe Von Neumann Architecture by John von Neumann. It is the responsibilty of the Control Unit to tell the computer's memory, arithmetic/logic unit and input end output devices how to respond to the instrictions that have been sent to the processor, It fetches internal instructions ofthe programs from the main memory to the processor instruction register, and based on this register Contents, the control unit generates 4 control signal that supervises the execution of these instructions, A control unit works by receiving input information to which it converts into control signals, which are then sent to the central processor, The computer's processor then tells the atached hardware what operations to perfonm. The functions that a control unit performs are dependent on the ‘ype of CPU because the architecture of CPU varies from manufteturer to manufacturer Examples of devices that require a CU are: 2Conta signals Control Within CPU Bus. 3 Contra signals trom Control bus ee ‘Contra signals to Control bus 1 Block Diagram of the Control Unit Functions of the Control Unit — 1. Teoordinates the sequence of data movements into, out of, and between a processor's many sub-unit. 2. It interprets instructions, 3. It controls data flow itiside the processor. ‘4. It receives external instructions or commands to which it converts to sequence of control signals, 5. Ieontrols many execution units(ie. ALU, data buffers and registers) contained within a CPU. 6. It also handles multiple tasks, such as fetching, decoding, execution handling and storing results. ‘Types of Control Unit — ‘There are two types of control units: Hardwired control unit and Micro-programmable control unit, 1, Hardwired Control Unit In the Hardwired contol uni, the control signals that are important for instruction execution control are generated by specially designed hardware logical circuits, in which we ean not ify the signal generation method without physical change of the eireuit structure, The operation code of an instruction contains the basic data for control signal generation. In the instruction decoder, the operat n code is decoded, The instruction decoder constitutes a set of many decoders that decode different fields of the instruction opcode, FyCOA Notes 3" Year CSE Dr. Rajender Kumar AS aresul, few output lines going out from the instruction decoder obtains active signal ates control values, These output lines are connected to the inputs of the matrix that gene Signals for exeeutive units of the computer. This matrix implements logical combinations of the decoded signals from the instruction opcode with the outputs from the matrix that Benerates signals representing consecutive control unit states and with signals coming f the outside of the processor, eg. interrupt signals. The matrices are builtin similar way as 4 programmable logic arrays. (Cescose | Aaaess Fe] Rectangular signal mstucton 7] From quartz decoder generator | | | [| 2. Contrat signal | _——-[scamate J} — Ssh see “Signal i Generation sh mat Flags and | exer variables Sanus Block diagram of a hardwired control unit of a computer ————e Control signals for an instruction execution have to be generated not in a single time point | | | | but during the entire time interval that corresponds to the instruction execution cycle. Following the structure of this cycle, the suitable sequence of internal states is organized in the control unit, A number of signals generated by the control signal generator matrix are sent back to inputs ofthe next control state generator matrix. This matrix combines these signals with the timing signals, which are generated by the timing unit based on the rectangular pattems usually supplied by the quartz generator. When a new instruction arrives at the control unit, the control units is in the initial state of new instruction fetching. Instruction decoding allows the control unit enters the first state relating execution of the new instruction, which Jasts as long as the timing signals and other input signals as flags andi state information of the computer remain unaltered. A change of any of the earlier mentioned signals stimulates the change of the control unit state.Dr. Rajender Ki COA -Notes 3" Year CSE yr. Rajender Kum ‘This causes that a new respective input is generated for the control signal generator matrix, When an external signal appears, (¢.g. an interrupt) the control unit takes entry into a next control state that is the state concerned with the reaction to this external signal (eg. interrupt Processing). The values of flags and state variables of the computer are used to select Suitable states for the instruction execution cycle. Micro programmable control unit = ‘The fundamental difference between these unit structures and the structure ofthe hardwired control unit is the existence of the control store that is used for ‘storing words containing encoded control signals mandatory for instruction execution. In micro-programmed control ‘nits, subsequent instruction words are fetched into the instruction register in a normal way. However, the operation code of each instruction is not directly decoded to enable immediate ignal generation but it comprises the initial address of a micro-program contained in the control store. control + With a single-level control store: mn this, the instruction opcode from the instruction register is sent to the control store address register. Based on this address, the first microinstruction of a micro-program that interprets execution of this instruction is read to the microinstruction register. This microinstruction Contains in its operation part encoded control signals, normally as few bit fields. In a set microinstruction field decoder, the fields are decoded. The microinstruction also contains the address of the next microinstruction of the given instruction micro-program and a control field used to control activities of the microinstruction address generator. Micoinsrusion From main garess monary regeer =] y ‘Opcode [Address ie instruction register Aucronsmuction regsier sae eran WAN a aoe sical meow Conve! signals Microprogrammed control unit with a single level control store 26COA Notes 3" Year CSE ; Dr. Rajender Kumar The last mentioned field decides the addressing mode (addressing operation) to be applied to the address embedded in the ongoing microinstruction. In microinstructions along with conditional addressing mode, this address is refined by using the processor condition flags that represent the status of computations in the current program. The last microinstruction in the instruction of the given micro-program is the microinstruction that fetches the next instruction from the main memory to the instruction register. With a two-level control store: In this, ina control unit with a two-level control store, besides the control memory for . nicroinstructions, a Nano-instruction memory is included. In such a control unit microinstructions do not contain encoded control signals, The operation part of ‘microinstructions contains the address of the word in the Nano-instruction memory, which contains encoded control signals. The Nano-instruction memory contains all combinations of control signals that appear in micro-programs that interpret the complete instruction set of @ given computer, written once in the form of Nano-instructions. Mieroinsiruction From man faderess" memory ‘Opeoee se eronseten [SsaraTT ares) MS cect Kae Eten | ‘Control signals encoded in nanoinstructon words Microprogrammed control unit with a two-level control store MICRO PROGRAM SEQUENCER ‘Micro Program Sequencer is a combination of all hardware for selecting the next micro- instruction address. The micro-instruction in control memory contains’a set of bits to initiate Tnicro operations in computer registers and other bits to specify the method by which the address is obtained. aCOA Notes 3 Year CSE Implementation of Miero Program Sequencer ~ Instruction Cone Conteo! Memory + Control Address Register(CAR) : Control address register receives the address from four different paths. For receiv addresses from four different paths, Multiplexer is used. + Multiplexer ; Muhiplexer is a combinational circuit which contains many data inputs and single dats ourpst depending on control or select inputs. + Branching : Branching is achieved by specifying the branch address in one of the fields of the micro instruction. Conditional branching is obtained by using part of the micro-instruction to select 2 specific status bit in order to determine its condition. + Mapping Logie : ‘An external address is transferred into control memory via a mapping logis circuit. + Incrementer t TInctementer increments the content of the control address register by one, to select the next micro-instruction in sequence. + Subroutine Register (SBR) : ‘The return address for a subroutine is stored in a special register called Subroutine Regist: ‘hose value is then used when the micro-program wishes to return from the subroutine, + Control Memory : Control memory is a type of memory which conteins addressable storage registers. Data is Dr. Rajonder Kung ¥COA -Notes 3" Year CSE Dr, Rajender Kumar temporarily stored in control memory. Control memory can be accessed quicker than main memory, HARDWIRED VS MICROPROGRAMMED CONTROL UNIT To execute an instruction, there are two types of control unit, 1, Hardwired control units are generally faster than micro-progra control, we saw how all the control signals required inside the CPU can be immed designs. In hardwired generated using a state counter and a PLA (Programmable Logic Array) circuit. 2, A micro-programmed control sequencing through microinstructions and (2) microinstruction, unit is a relatively simple logic circuit that is capable of (1) generating control signals to execute each Hardwired Control Unit Micro-programmed Control Unit Hardwired control unit generates the control signals needed for the processor using logic circuits Micro-programmed control unit generates the control signals with the help of micro instructions stored in control memory Hardwired control unit is faster when compared to micro-programmed control unit asthe required control signals are generated with the help of hardware’s ‘This is slower than the other as micro instructions are used for generating signals here Difficult to modify as the control signals that rieed to be generated are hard wired Easy to modify as the modification need to be done only at the instruction level More costlier as everything has to be realized in terms of logic gates Less costlier than hardwired control as only micro instructions are used for generating control signals It cannot handle complex instructions as the circuit design for it becomes complex. Itcan handle complex instructions Only limited number of instructions are used due to the hardware implementation Control signals for many instructions can be generated Used in computer that makes use of Reduced Instruction Set Computers(RISC) Used in computer that makes use of Complex Instruction Set Computers(CISC) 29