a COA Notes 3" Yoar CSE Dr. Rajender Kumar. UNIT-IL Basic Computer organization and Design: Instruction codes, stored program organization, instructions, timing and control, instruction computer registers and common bus system, comput cycle: Fetch and Decode, Register reference instruction: Register reference instructi mn, instructions, Program interrupt, Interrupt cycle, Micro- Memory reference instructions. Input, output and Interrupt configur programmed Control organization, Control Memory, address sequencing, Micro program Example, micro instruction format, Horizontal Vs Vertical micro-programming, design of control Unit, micro program sequencer, Hardwired v/s Micro-Programmed Control Unit COMPUTER ARCHITECTURE: INSTRUCTION CODES ice An instruction code is a group of bits that instruct the computer to perform a specific operation. The operation code of an instruction ig a group of bitS that define operations such as addition, subtraction, shift, complement, ete. An instruction must-also include one or more operands, which indicate the registers and/or memory addresses froin, whic. data is taken or to which data is deposited. ‘Micro-operations-The instructions are stored in computer memory in the same mariter that data is stored. The control unit interprets these instructions and uses the operations code to determine ‘the sequences of micro-operations that must be performed to execute the instruction. Instruction Code: Operation Code™ “The operation tode of an iisfruction is a group of bits that define operations such as add, subtract, multiply, shift and compliment. The number of bits required for the operation code depends upon the total umber of operations available on the computer. The operation code ntust consist of at least n bits for a given 24n operations, The operation part of an instruction code specifies the operation to be performed, Instruction Code: Register Part ‘The operation must be performed on the data stored in registers. An instruction code therefore specifies not only operations to be performed but also the registers where the operands(data) will bbe found as well as the registers where the result has to be stored. cesreeeeeenoseegeaeseseoeeeseaeeeeeteeoeererv eeCOA -Notes 3 Year CSE Dr. Rajender Kumar STORED PROGRAM ORGANIZATIOI ‘The operands are specified by indicating the registers and/or memory locations in which they are stored. ~k bits can be used to specify which of 2k registers (or memory locations) are to be used. The simplest design is to have one processor register (called the accumulator) and two fields in the instruction, one for the opcode and one for the operand. Any operation that does not need a memory operand frees the other bits (o be used for other purposes, such as specifying different operations. The simplest way to organize a computer is to have Processor Register and instruction code with two parts, The first part specifies the operation to be performed and second specifies an address. ‘The memory address tells where the operand in memory will be found. Instructions are stored in one section of memory and data in another. Computers with a single processor register is known as Accumulator (AC). The operation is performed with the memory operand and the content of AC. ERS MON BUS SYST! RE comput! Registers are a type of computer memory used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. The registers used by the CPU are often termed as Processor registers. SIPGKEEHEESCRCHHLHOFHH CER HHOHBEHEHHO RH HR HOH BBECOA -Notes 3 Year CSE A processor register may hold an instruction, a storage address, or any data (such or individual characters), The computer needs processor registers for manipulating data and a re address. The register holding the memory loc Dr. Rajender Kumar ag bit sequence jer for holding a memory ‘ation is used to calculate the address of the next instruction after the execution of the current instruction is completed. Following is the list of some of the most common registers used in a basic computer: Symbol Register Number of bits’ | Function Data register DR 16 Holds memory operand Address register AR 12 Holds address for the memory ‘Accumulator AC 16 Processor register Instruction register | IR 16 Holds instruction code Program counter PC 12, Holds address of the instruction Temporary register | TR 16 Holds temporary data Input register inpR | 8 Carries input character Output register ourr| 8 Carries output character The following image shows the register and memory configuration for a basic computer eeeveeetevovnesevuvaeCOA -Notes 3" Year CSE Dr. Rajender Kumar ° As _ - ° gister and Memory Configuration of a basic computer: | oe . | 9 eaeaten a =| 9° Memory | 4096 words: ° . 8Biesetioe || > 1s if las (hear TINBR ‘The Memory unit has a capacity of 4096 words, and each word contains 16 bits. 4 ‘The Data Register (DR) contains 16 bits which hold the operand read from the memory location. ‘The Memory Address Register (MAR) contains 12 bits which hold the address for the memory location, The Program Counter (PC) also contains 12 bits which hold the address of the next instruction to be read from memory after the current instruction is executed. ‘The Accumulator (AC) register is a general purpose processing register. ‘The instruction read from memory is placed in the Instruction register (IR). ~_—-'- ese weseeeeegsgeseee2a2eedsdees @e The Temporary Register (TR) is used for holding the temporary data during the processing, ‘The Input Registers (IR) holds the input characters given by the user. © The Output Registers (OR) holds the output after processing the input data, COMMON BUS SYSTEM We shall study the common bus system ofa very basic computer in this article, A basic computer wae I SD £0 0 0 0 © © OO ONetehene- ore, 2.0) I! has 8 registers, memory unit and a control unit, To avoid excessive wiring, memory and all the ' register are connected via a common bus. The specific output that is selected for the bus is Y determined by $2S1S0. The register whose LD (Load) is enable receives the data from the bus. » 4 ’ ! 'COA -Notes 3 Year CSE Dr. Rajender Kumar Registers can be incremented by setting the INR control input and can be cleared by setting the CLR control input. The Accumulator’s input must come via the Adder & Logie Circuit. This allows the Accumulator and Data Register to swap data simultaneously. The address of any memory location being accessed must be loaded in the Address Register. Basic Computer Organization & Design 2 Registers COMMON BUS SYSTEM Outputs of the six registers and memory unit ere connected to the commom bus of 16 lines. The speciiic output is selected from the binary value of the selection variables $2, $1, $0. The lines from the common bus are connected to the inputs of each register and the datainput ofthe memory. The particular register whose LD (Load) input is enabled receives the data from the bus. INPR receives the a character from an input device and whichis then transferred to AC. OUTR receive the character from AC and delivers itto an output device. Computer Architectures Computer Organization COCHOHHCCHOHECEEOHHOHOHHHHHHHHHHHHHHHHHIIAMCOA -Notes 3" Year Cgp der Kumar Connections: The outputs of all the registers except the OUTR (output register) are connected to the common bus. The output selected depends upon the binary value of variable 2, $1 and SO, The lines from. common bus are connected to the inputs of the registers and memory. A register receives the information from the bus when its LD (load) input is activated while in case of memory the Write input must be enabled to receive the information, The contents of memory are placed onto the bus when its Read input is activated, Various Registers: 4 registers DR, AC, IR and TR have 16 bits and 2 registers AR and PC have 12 bits. The INPR and OUTR have 8 bits each. The INPR receives character from input device and delivers it to the AC while the OUTR receives character from AC and transfers it to the output’deVvice. 5 registers have 3 control inputs LD (load), INR (increment) and CLR (clear). These types of registers are similar to a binary counter. i a Abbreviation Register name OUTR ~ | Output register TR Temporary register IR Tnstruction register INPR, Input register AC * Accumulator DR Data register PC. a | Program counter AR ‘Address register Adder and logic circuit: The adder and logic circuit provides the 16 inputs of AC, This circuit has 3 sets of inputs, One set comes from the outputs of AC which implements register micro operations. The other set comes from the DR (data register) which are used to perform arithmetic and logic micro operations. The result of these operations is sent to AC while the end around carry is stored in E as shown in diagram. The third set of inputs is from INPR. eee eeceeeeeeee ee eeeoeeeH7eeFe2HHH 009 9‘CoA Notes 3" Year CSE Dr. Rajender Kumar COMPUTER INSTRUCTIONS Computer instructions are a set of machine language instructions that a particular processor understands and executes, A computer performs tasks on the basis of the instruction provided. An instruction comprises of groups called ficlds. ‘These fields include: The Operation code (Opeode) field which specifies the operation to be performed, 9 The Address field which contains the location of the operand, ic., register or memory location. © The Mode field which specifies how the operand will be located ‘A basic computer has three instruction code formats which are: rote [ope | che ba 1. Memory - reference instruction 2. Register - reference instruction woes Inghuchiow ~ 3. Input-Output instruction CA- Memory - reference instruction Pome aon © 1 — MEMORY ADDRESS In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the addressing mode" Memory Reference ~ These instructions refer to memory address as an operand. The other operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and L-bit addressing mode for direct and indirect addressing. ial Example IR register contains = 0001XXXXAXXXXAXX, ie. ADD after fetching and decoding of instruction we find out that it is a memory reference instruction for ADD oj ti DD operation. Bs es ee @ oe 6 Oe 8 8 were e988 0 8260 6A -Notes 3" Year CSE, Dr. Rajender Kumar DR = M[AR] AC — AC + DR, SC —0 Basie Memory-Reference Instructions [ymbol Operation Decoder [Symbolic Description ND ID) ee JAC — AC A MAR] ADD (Dr ACH MAR] =, E = Cou DA= [Dz JAC — M[AR] Bra = [Ds [AR] — AC BUN [Dv ey PC —AR ipsa Ds fAR] — PC, PC—AR+1 oe AR] — MIAR] + 1, lsz IDs FM[AR] +1=Othen PC —PC+1 a aga REGISTER OPERATION “The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit 15) of the instruction. ‘A Register-reference instruction specifies an operation on or a test of the AC (Accumulator) register. Register Reference — These instructions perform operations on registers rather than memory addresses. The IR(14 — 12) is 111 (differentiates it from memory reference) and IR(1S) is 0 (differentiates it from input/output instructions). The rest 12 bits specify register operation. Example IR register contains = 0111001000000000, i.e. CMA after fetch and decode cycle we find out that it isa register reference instruction for complement accumulator, Hence, AC — ~AC at sss ae S@eSGeSC OCC CeCe eds de ss Pes vv F FY VG ZGoe 3, “COA Notes 3 Year CSE Dr. Rajender Kumar Input-Output instruction 16 ta 12011 0 4-4 hd INPUTIOUTPUT OPERATION to memory and is recognized by the operat instruction. The remaining 12 bits are used to specify the type of the input-output operation or test , performed. Input/output environment. The IR (14 ‘These instructions are for communication between computer and out Just like the Register-reference instruction, an Input-Output instruction does not need a reference tion code 111 with a 1 in the leftmost bit of the side = 10) is 111 (differentiates it from memory reference) and IR (15) is 1 (differentiates it from register reference instructions). The rest 12 bts specify VO operation. Example IR register contains = 1111100000000000, i. INP after fetch and decode cycle we find out that it is an input/output instruction for inputting charac device. ter. Hence, INPUT character from peripheral ‘The set of instructions incorporated in16 bit IR register are: ‘Arithmetic, logical and shift instructions (and, add, complement, circulate left, right, ete) 2. To move information to and from memory (store the accumulator, load the accumulator) 3, Program control instructions with status conditions (branch, skip) 4, Input output instructions (input character, output character) Note o The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise, the instruction is a memory-reference type, and the bit in position 15 is taken as the addressing mode I ® a CSPCSCHSHSOSBHEHEHBOHOOFEHCHLOBEAHHTEBEHKeH HEHE DDAOOOSOFe Notes 3"! Yenr CSE cos Notes 3" Year CSE. Dri Rajesder Kumar 9. When the three operation code bits are e4 5 0, the instruction fs a register-reference type. Otherwise, the qual to IIL, control unit inspects the bit in position 15, If the bit instruction isan inpnt-outul type having bit 1 at position 15. AZIMING. AND CONTROL suo bse [AIL sequential cireuits in the Basie Comput wer CPU are driven by a master clock, with the exception of the INPR register. [At-cach clock pulse, the control unit sends control signals to control inputs of the bus, the registers, and the ALU. Control unit design and implementation enn be done y evo general methods: 1 logic design techniques ditional d sired controlunit is designed from seratch using tra fhe control unit is like an ASIC A hardw rds, 15 to produce » minimal optimized circuit. In other wo (appliction-specific integrated circuit) strotunt is bu fom sone sort of ROM. The desired control signs 5 A microprogrammed co to drive the microoperations needed by a VS simply stored in the ROM, and retrieved in sequence particular instru INSTRUCTION C CLE ‘The instructions of a program are carried out by a process called the instruction cycle. _ Fetch an instruction from memory — Decode f the operand has an indirect address. — ‘The instruction cycle consists of these phases: the instruction — Read the effective address from memory i Execute the instruction. Initially, the PC has stored the address of the instruction about to be executed and the SC is + the SC is incremented and the timing signals go through the cleared to 0, With each clock pulses sequence TO, Tl, T2, ee, It is necessary to fond the AR withthe PC's address (itis connected to ‘memory address inputs); T0; AR “PC Subsequently, a8 we fetch the instruction to be executed, we must increment the program counter 0 that it points to the next instruction: TI; IR “ M[AR], PC ~ PC + I + In order to carry out the 10 ve a 2 e 3 3° a 2 3 3 ® 2 2 a e a Vy 3 ° =<0 _Notes 3"! Year CSE Dr. Rajender Kumar ipstruotion, we must deco: ‘ os de and ‘prepare to fetch the operand, In the event it is an indirect and, we need i \ operant eed to have the indirect addressing bit as well: T2: DO, ... D7 ~ Decode IR(12-14), ART IR (0-11), 1 IRUS) % ‘A program residing in the memory unit of a computer con: 1g through a cycle for each instruction. sists of a sequence of instructions. @0000000 "These instructions are executed by the processor by goin Inia basi¢ computer, each instruction cycle consists ofthe following phases: 1. Fetch instruction from memory. 2. Decode the instruction. 3. Read the effectivp address from memory. 4, Execute the instruction. | Instruction | cycle | |e @ @ @ @ @ @ @ @ @ @ @ @ INPUT-OUTPUT. JNFIGURATION terface between the machine and the In computer architecture, input-output devices act as an in user. and data stored in the memory must come from some input device. The results are Instructions .¢ output device. to the user through som ‘The following block diagram shows the input-output configuration for @ basic computer. 1 @n2e0e0800660080COA -Notes 3" Year CSE Dr. Rajender Kuma Input - Output Contiguration: Input-Output Terminal Serlal Communteatton Computer registers Intertace & Flip Flops i wba} Aieassy a oma iasteeetiad ‘The input-output terminals send and receive information. | 1 rf The amount of information transferred will always have eight bits of an alphanumeric code. ‘The information generated through the Keyboard is shifted into an input register TNPR’, The information forthe printer is stored inthe output register ‘OUTR, Registers INPR and OUTR communicate with a communication in We AC in paraltel, ‘The transmitter interface recei information from the keyboard and transmits it to INPR. The receiver interface receives information from OUTR and sends it to the printer serially. Design of a Basic Computer A basic computer consists of the fallowing hardware components, 2. sen A memory unit with 4096 words of 16 bits each Registers: AC (Accumulator), DR (Data register), AR-(Address register), UR (lnstructo register), PC (Program counter), TR (Temporary register), (Input register), and OUTR (Ouput register), SC (Sequence Counter), INP Flip-Flops: 1, 8, B, R, IEN, FGI and EGO Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder A 16-bit common bus Control Logic Gates The Logic and Adder circuits connected to the input of AC, terface serially and with n R 2 o9 ss eee8eeeeneeeeeeenns seeeeseoes9989°82COA -Notes 3° Year CSE Dr. Rajender Kumar Computer Organization | Basic Computer Instructions The basic computer has 16-bit instruction register (IR) which can denote either memory reference or register reference oF input-output instruction. AM INTERRUPT; Program interupt defines the transfer of program control from a currently running program to ‘nother service program as a result ofan external or intemal created request. Control returns to the initial program after the service program is implemented. ‘There are three major types of program interrupts that are as follows — External Interrupts Extemal interupts come from input-output (V0) devices, from a timing device, fom a circuit ‘monitoring the power supply, or from any other extemal source. The timeout interrupt can result fom a program that is in,an endless loop and thus exceeded its time allocation. Power file intemupt can have as its service routine a program that transfers the complete state ofthe CPU into non-destructive memory in a few milliseconds before power ceases, Internal Interrupts Interal interrupts arse from illegal or erroneous tse ofan instruction or data Internal interrupts ‘re also called traps. These error conditions generally appear asa result of premature termination of the instruction execution. The service program that processes the internal interrupt determines the corrective measure to be taken, ‘The main diference between intemal and extemal interrupts is tht the internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an extemal event. Intemal interrupts are synchronous with the program while ext femal interrupts. are asynchronous. Ifthe program is rerun, ‘he internal iaterupts will appear in the same place each time. External interrupts depend on external conditions that are in lependent of the program being ‘executed atthe time. Software Interrupts B eoevseereeeeceeeoeeeeesex2sesree2 00000000080 |,Be Od : 32 RG L : % 2%. COA-Notes 3 Dr. Rajender Kumar Bee : Sheila ZF QA software interrupt is initiated by executing an instruction. A software interrupt is @ special call instruction that behaves like an interrupt rather than a subroutine call. It can be used by the AZ) programmer to initiate an interrupt procedure at any desired point in the program. S INTERRUPT CYCLE + An instruction cycle (sometimes called fetch-and-exccute cycle, fetch-decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a ‘computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from boot up to when the computer is shut down. r é | Fateh Cycle Execute Cycle Interrupt Cyl | . i | | Block diagram of Interrupt Cycle + After the execute cycle is completed, a test is made to determine if an interrupt was enabled (¢.g, so that another process can access the CPU) + If not, instruction eycle returns to the fetch eycle + If so, the interrupt cycle might perform the following tasks: (simplified...) move the current value of PC into MBR + move the PC-save-address into MAR 4 4 SFT SL 52S CCH CCHOTHO®VGFGFGFXDVO HL HOH VHF XLHOKOHHHD19303 COA -Notes 3" Year CSE Dr. Rajender Kumar \ si onen oe i Toner Hs % ‘ & & move the interrupt-routine-address into PC ‘move the contents of the address in MBR into indicated memory cell continue the instruction eyele within the interrupt routine after the interrupt routine finishes, the PC-save-address is used to reset the value of PC and program execution ean continue Bhp Nek ef Sone rune Figur + Flowchart of interrupt cycle MICRO-PROGRAMMED CONTROL ORGANIZATION: A control unit whose binary control values are saved as words in memory is called microprogrammed control unit. 35\ snug $1019 ~veasus pu 5 ( COA -Notes 3° Year CSE Dr. Rajender Kumar ‘A controller results in the instruct ns to be implemented by constructing a definite collection of signals at each system clock beat. Each of these output ignals generates one micro-operation yeh i register transfer. Thus, the sets of control signals are generated definite micro- operations that can be saved in the memory, Each bit that forms the microi ruction is linked to one control signal. When the bit is set, the control signal is active. When it is cleared the control signal turns inactive. These microinstruction in a sequence can be saved in the internal ‘control’ memory. The control unit of a microprogram-controlled computer is a computer inside a computer. ‘The following image shows the block diagram of a Microprogrammed Control orga Micro Programmed Control Organization 9 Controt Word § There are the following steps followed by the microprogrammed control are — It can execute any instruction. The CPU: should divide it down into a set of sequential operations. This set of operations aré called microinstruction. The sequential micro- operations need the control signals to execute. Control signals saved in the/ROM are created to execute the instructions on the data direétion. These, control signals can control the micro-operations concerned with a microinstruction that is to be performed at any time step. ‘The address of the microinstruction is executed next is generated, The previous 2 steps are copied until all the microinstructions associated with the instruction in the set are executed, ‘The address that is supported to the control ROM originates from the micro counter register. The micro counter received its inputs from a multiplexer that chooses the output of an address ROM, @ current address Incrementer, and an address that is saved the next address field of the current microinstruction. Advantages of Microprogrammed Control Unit 16 rr ar i ae ee ee ee ee ee4 COA -Notes 3" Year CSE Dr. Rajender Kumar ~asoaut OY There are the following advantages of microprogrammed control are as follows — + Itecan more systematic design of the control unit. + Itis simpler to debug and change. + Itcan retain the underlying structure of the control function, + Itcan make the design of the control ur much simpler. Hence, it is inexpensive and less error-prone. + It can orderly and systematic design process. + Itis used to control functions implemented in software and not hardware. +, Itis more flexible and used to complex function is carried out easily. Disadvantages of Microprogrammed Control Unit There are the following disadvantages of microprogrammed control are as follows — + ‘Adaptability is obtained at more cost. + Itis slower than a hardwired control unit. CONTROL MEMORY: A control memory is a part of the control unit. Any computer that involves microprogrammed control consists of two memories. They are the main memory and the control memory. Programs are usually stored in,thé main memory by the users. Whenever the programs change, the data is also modified in the main methory. They consist of machine instructions and data. The control memory consists of microprograms that are fixed and cannot be modified frequently. y consisis}of x rams that They contain’ microinstructions that specify the internal control signals required to execute register - eer micrd-operations. The machine instructions generate a chain of microinstructions in the control memory. Their function is to generate micro-operations that can fetch instructions from the main memory, 4 compute the effective address, execute the operation, and retum control to fetch phase and continue the cycle, Here, the control is presumed to be a Read-Only Memory (ROM), where all the control information is stored permanently, ROM provides the address of the microinstruction. The other register, that is, the control data register stores the microinstruction that is read from the memory. It consists of a control word that holds one or more micro-operations for the data processor. 17)COA -Notes 3" Year CSE Dr. Rajender Kumar The next adres must be computed once this operation is complete. It is computed in the next address generator, Then, itis sent to the control address register to be read, The next addess esnerator i also known asthe mietoprogsam sequenect. Based onthe inputs toa sequent it detemiines the address of the next microinstruction. ‘The microinstructions can be specified in ys several \ ADDRESS SEQUENCING Microinstructions are saved in control memory in groups. These groups describe routines, Each ‘computer instruction has its microprogram routine that can create micto-operations, These micro- operations can execute instructions, The hardware consists of controls for the address sequencing of the microinstructions of a similar routine, They also branch the microinstructions. There are the following phases that the control, has while implementing a computer instruction — ‘When power is turned on, and address is initially loaded into the control address register, (This is the address of the fist microinstruction). The control address register is incremented resulting in sequencing the fetch routine. After the fetch routine, the instruction is present in the IR of the computer. Next, the control memory rettieves the effective address of the operand from the routine. ‘Thus, the mapping process appears from thé instruction bits to a control memory address. + It depends on the opcodes of instruction the microinstructions of the processor registers are generated, Each of these inicroinstructions has a separate microprogram routine stored. The instruction code bits are changed into the address where the routine is placed and is known as the mapping process. A mapping process transforms the microinstruction into a control memory address. + Next, subroutings are called and processes are returned,a fo MOTAS sousd amp FO MOF Somerorgy UL ‘5? os \ 4 / COA -Notes 3“ Year CSE Dr. Rajender Kumar After the completion of the routine, the control address register is incremented to sequence the instrnction is imnlemented. Selection of Address for Control Memory [Subroutine Register (SBR) -—__J Incrementer Multiplexers. Selecta Status Bit Control Address Register (CAR) Clock —> / Aoweyi jonuos Micro operations The diagram shows the block diagram of a.control memory and its associated hardware to support in choosing the next microinstruction. The microinstruction present in the control memory has a set of bits that facilitate.to'start off the micro-operations in registers. ‘There are four different directions are showed in the figure from where the control address register recovers its address. The CAR is incremented by the incrementer and selects the next instruction. In multiple: fields of- microinstruction, the branching address can be determined to result in branching. It can specify the condition of the status bits of microinstruction, conditional branching can be applied. A mapping logic circuit can share an external address, A special register can save the retumn address so that when the microprogram needs to return from the subroutine, it can need the value from the unique register, MICRO INSTRUCTION FORMAT A microinstruction format includes 20 bits in total. They are divided into four elements as displayed in the figure. woeeeeoceecsc eevee oveeeers ee see esesessevsencd COA -Notes 3" Year CSE Dr. Rajender Kumar oa ~~ Mieroinstruction Code Format ee Saar 3 3 3 2 2 7 | 2 FL F2 a ee AD, FI, F2, F3 are the micro-operation ficlds, They determine micro-operations for the computer. CD is the condition for branching. They choose the status bit conditions. BR is the branch field. It determines the type of branch, AD is the address field. It includes the address field whose length is 7 bits, The two widely used formats employed for micro-instructions are vertical and horizontal, In horizontal micro-instruction every bit of micro-instruction signifies a control ignal that directly controls a single bus line or occasionally a gate in the machine. Though the length of such a micro-instruction can be hundreds of bits. A typical horizontal micro-instruction with its related fields is demonstrated in Figure below. [reiviguat control | sigral for emernat CPU contol A microinstruction Jump conditions ‘Microinstraction branch address (unconditional zero, ‘overflow, indirect) | (a) Horizontal Micro-instruction Ina vertical micro-instruction several similar control signals can be encoded in a few micro- instruction bits. For example, for 16 ALU operations that may need 16 individual control bits in horizontal microinstruction only 4 encoded bits are required in vertical micro-instruction. In the some way in a vertical micro-instruction only 3 bits are required to select one of eight registers. Though these encoded bits need to be passed from the respective decoders to get the individual control signals, 20 -SaMeenanannaneaneannnaaeaseav se See HST HHH STW,oa Notes 3° Year CSE Dr. Rajender Kumar ta (b) Vertical Micro-instructions ESIGN OF CO! UNIT Control Unit is the part of the computer's central processing unit (CPU), which directs the operation of the processor. It was included as part of the Von Neumann Architecture by John von Neumann, It is the responsibility of the Control Unit to tell the computer's memory, arithmetic/logie unit and input and output devices how to respond to the instructions that have been sent to the processor. It fetches internal instructions of the programs from the main memory to the processor instruction register, arid based on this register contents, the control unit generates ‘ control signal that supervises the execution of these instructions, ‘A control unit works by receiving input information to which it converts into control signals, which are then sent to the central processor. The computer’s processor then tells the attached hardware what operations to perform. The functions that a control unit performs are dependent on ‘the type of CPU because the architecture of CPU varies from manufacturer to manufacturer. Examples of devices that require a CU are: a »>eoe eee eee e ee ee vee eee ere eerste wrsrersrssveon/ on “Notes 3° Year CSE Dr. Rajender Kumar Control signats within CPU. Controt eo Bus Control signats trom Gontet bu! Control signals to | ena | | —| | | \ Block Diagram of the Control Unit Functions of the Control Unit - 1. Itcoordinates the sequence of data movements into, out of, and between a processor's many sub-units. 2. It interprets instructions. 3. Itcontrols data flow inside the processor. 4, Itreceives external instructions, or,commands to which it converts to sequence of control signals. 5. Itcontrols many execution units(i.e. ALU, data buffers and registers) contained within a CPU. 6. Italso handles multiple tasks, such as fetching, decoding, execution handling and storing results. ‘Types of Control Unit — ‘There are two types of control units: Hardwired control unit and Microprogrammable control unit. 1. Hardwired Control Unit — In the Hardwired control unit, the control signals that are important for instruction execution control are generated by specially designed hardware logical circuits, in which we can not modify the signal generation method without physical chango of the circuit structure. The operation code of an instruction contains the basic data for control signal generation. In the instruction decoder, the operation code is decoded. The instruction decoder constitutes a set of many decoders that decode different fields of the instruction opcode, As a result, few output lines going out from the instruction decoder obtains active signal values. These output lines are connected to the inputs ofthe matrix that generates control 22we Dr. Raj " ; + Rajender Kumar signals for executive units of the computer. This matrix implements logical combi i combinatic the decoded signals from the instruction op. mist ode with the outputs from the matrix that generates signals representing consecutive control unt states and with signals comi f ing from the outside of the processor, e.g, interrupt signals. The matrices are builtin a simita Way as a programmable logic arrays, 4 | Rectangular signal | From quartz oe Be Contras signat |}—~ Forrnar [= computer Control signals for an instruction execution have to be generated not in a single time point ‘but during the entire time interval that corresponds to the instruction execution cycle. Following the structure of this cycle, the suitable sequence of internal states is organized in the control unit. A number of signals generated by the control signal generator matrix are sent back to inputs of the next control state generator matri . This matrix combines these signals with the timing signals, which are generated by the timing unit based on the rectangular patterns. usually supplied by the quartz generator, When a new instruction arrives at the control unit, the control units is in the initial state of new instruction fetching. Instruction decoding allows the control unit enters the first state relating execution of the new instruction, which lasts as Jong as the timing signals and other input signals as flags and state information of the computer remain unaltered. A change of any of the earlier mentioned signals stimulates the change of the control unit state. ‘This causes that a new respective input is generated for the control signal generator matrix. When an external signal appears, (¢.g. an interrupt) the control unit takes entry into a next control state that is the state concerned with the reaction to this external signal (e.g. interrupt po we eo wre rwcOA-Notes 3" Year CSE. Dr. processing). The values of flags and state variables of the computer are u; suitable states for the instruction execution cycle, Rajender Kumar sed to select Micro programmable control unit — The fundamental difference between these unit structures and the structure of the hardwired control unit is the existence of the control store that is used for storing words containing encoded control signals mandatory for instruction execttion.In microprogrammed control units, subsequent instruction words are fetched into the instruction register in a normal way. However, the operation code of each instruction isnot ditcetly decoded to enable immediate control signal generation but it comprises the initial address of a microprogram contained in the control store. » With a single-level control store: In this, the instruction opcode from the instruction register is sent to the control store address register. Based on this address, the first microinstruction of a microprogram that interprets execution of this instruction is read to the microinstruction register. This microinstruction contains in its operation part encoded control signals, normally as few bit fields. In a set microinstruction field decoder, the fields are decoded. The microinstruction also contains the address of the next microinstruction of the given instruction microprogram and a control field used to control activities of the microinstruction address generator. [ ; Be “igrene oo" ficroprogrammed control unit with a single level control store ‘The last mentioned field decides the addressing mode (addressing operation) to be applied to the address embedded in the ongoing microinstruction. In microinstructions along with conditional addressing mode, this address is refined by using the processor condition flags that represent the status of computations in the current program. The last microinstruction in the instruction of the given microprogram is the microinstruction that fetches the next instruction from the main memory to the instruction register, 24 SSSCSCSCCKUCBUELYEYHYHBHHHvDD DO VEE Y YY YY, ,9ouuDr. Rajender Kumar In this, in a control unit with a two-level control store, besides the control memory for included. In such a control unit, microinstructions, a Nano-instruction memory. microinstructions do not contain encoded control signals. The operation part of microinstructions contains the address of the word in the ‘Nano-instruction memory, which contains encoded control signals. The Nano-instruction memory contains all combinations of control signals that appear in microprograms that interpret the complete instruction set of ions. From main a given computer, written once in the form of Nano-instruct microinstruction ‘aaarese, 1 ¥ Y | eno! signais encoded in nanoinstruction words Microprogrammed control unit with & two-level contro! store: MICRO PROGRAM SEQUENCER Micro Program Sequencer is a combination of all hardware for selecting the next micro- instruction address, The micro-instruction in control memory contains a set of bits to initiate micro operations in computer registers and other bits to specify the method by which the address is obtained. Implementation of Micro Program Sequencer — oeou”d “oO” O06 OO OUP OPEe Ueeteb UD UUUUVBDUVU DV UU VYf COA Notes 3" Year CSE Dr. Rajender Kumar Gontyor Adurase Wontar Control Memory Select staueon Branch Address + Control Address Register(CAR) : Control address register receives the address from four different paths. For receiving the addresses from four different paths, Multiplexer is used. + Multiplexer : Multiplexer is a combinational circuit which contains many data inputs and single data output depending on control or select inputs. : + Branching = : Branching is achieved by specifying the branch address in one of the fields of the micro instruction. Conditional branching is obtained by using part of the micro-instruction to select a specific status bit in order to determine its condition. + Mapping Logic : ‘An external address is transferred into control memory via a mapping logic circuit. + Incrementer z Incrementer increments the content of the control address register by one, to select the next micro-instruction in sequence. + Subroutine Register (SBR) : ‘The return address for a subroutine is stored in a special register called Subroutine Register whose value is then used when the micro-program wishes to return from the subroutine. + Control Memory : Control memory is a type of memory which contains addressable storage registers. Data is temporarily stored in control memory. Control memory can be accessed quicker than main memory. 26 PO SOTO HOHOHHOHHHHHHMAOHHOSEOBIIVIITIFOOOeO®Epe. 6 COA -Notes 3" Year CSE Dr, Rajender Kumar © f HARDWIRED VS MICROPROGRAMM! D CONTROL UNIT . To execute an instruction, there are two types of control unit, e 1. Hardwired control units are generally faster than microprogrammed designs. In hardwired » control, we saw how all the control s ignals required inside the CPU can be generated using a State counter and a PLA (Programmable Logic Array) ireuit, ‘A microprogrammed control unt is a relatively simple logic circuit that is capable of (1) sequen roinstruction, 1 through microinstructions and (2) generating control signals to execute each Hardwired Control Unit Microprogrammed Control Unit Hardwired control unit generates the control signals ‘needed for the processor using logic circuits Microprogrammed control unit generates the control signals with the help of micro instructions stored in control memory Hardwired control unit is faster when compared to microprogrammed control unit as the required control signals are generated with the help of hardware’s This is slower than the other as micro instructions are used for generating signals here Difficult to modify as the control signals that need to be generated are hard wired Easy to modify as the modification need to be done only at the instruction level More costlier as everything has to be realized in terms of logic gates Less costlier than hardwired control as only 1iero instructions are used for generating control signals It cannot handle complex instructions as the circuit design for it becomes complex Itcan handle complex instructions Only limited number of instructions are used due to the hardware implementation Control signals for many instructions can be generated Used in computer that makes use of Reduced Instruction Set Computers(RISC) Used in computer that makes use of Complex Instruction Set Computers(CISC) Fa ma» ©€02e CeO @ OG VG OH GCeAeoOodHHeOBOSEHHSB