Hardware Description Language (VHDL) :-
The VHSIC Hardware Description Language (VHDL) is a hardware description
language (HDL) that can model the behaviour and structure of digital systems at
multiple levels of abstraction, ranging from the system level down to that of logic gates, for
design entry, documentation, and verification purposes.
In 1983, VHDL was originally developed at the behest of the U.S. Department of Defense in
order to document the behaviour of the ASICs that supplier companies were including in
equipment.
VHDL is generally used to write text models that describe a logic circuit. Such a model is
processed by a synthesis program, only if it is part of the logic design.
A simulation program is used to test the logic design using simulation models to represent
the logic circuits that interface to the design. This collection of simulation models is
commonly called a testbench.
VHDL has constructs to handle the parallelism inherent in hardware designs.
VHDL has file input and output capabilities, and can be used as a general-purpose
language for text processing, but files are more commonly used by a simulation testbench
for verification data.
A final point is that when a VHDL model is translated into the "gates and wires" that are
mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual
hardware being configured, rather than the VHDL code being "executed" as if on some
form of a processor chip.
Advantages
The key advantage of VHDL, when used for systems design, is that it allows the behavior
of the required system to be described (modeled) and verified (simulated) before synthesis
tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system.
Concurrent System. In computer science, concurrency is the ability of different parts or
units of a program, algorithm, or problem to be executed out-of-order or in partial order,
without affecting the outcome. This allows for parallel execution of the concurrent units,
which can significantly improve the performance of digital system.
A VHDL project is portable. Being created for one element base, a computing device
project can be ported on another element base, for example VLSI with various
technologies.
A big advantage of VHDL compared to original Verilog is that VHDL has a full type system.
Designers can use the type system to write much more structured code (especially by
declaring record types).
Standard Libraries:-
It is also referred as standard packages.
The IEEE Standard Package includes the following:
numeric_std:- It is a library package defined for VHDL. It provides arithmetic functions
for vectors. Overrides of std_logic_vector are defined for signed and unsigned
arithmetic. It defines numeric types and arithmetic functions for use with synthesis
tools.
std_logic_1164:- It describes the definitions of logic values to be used in electronic
design automation, for the VHDL hardware description language. Following are the
example of this packages.
o std_logic_arith:- This is the library that defines some types and basic
arithmetic operations for representing integers in standard ways.
o std_logic_unsigned:- This library extends the std_logic_arith library to
handle std_logic_vector values as unsigned integers.
o std_logic_signed:- This library extends the std_logic_arith library to handle
std_logic_vector values as signed integers.
o std_logic_misc:- This package defines supplemental types, subtypes, --
constants, and functions for the Std_logic_1164 Package
Design examples
In VHDL, a design consists at a minimum of an entity which describes the interface and
an architecture which contains the actual implementation. In addition, most designs import
library modules. Some designs also contain multiple architectures and configurations.
[1] A simple AND gate in VHDL would look something like:
-- (this is a VHDL comment)
/*
this is a block comment (VHDL-2008)
*/
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- this is the entity
entity ANDGATE is
port (
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end entity ANDGATE;
-- this is the architecture
architecture RTL of ANDGATE is
begin
O <= I1 and I2;
end architecture RTL;
(Notice that RTL stands for Register transfer level design.)
[2] The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in
hardware design. The example below demonstrates a simple two to one MUX, with
inputs A and B , selector S and output X . Note that there are many other ways to express
the same MUX in VHDL.
X <= A when S = '1' else B;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port(
a1 : in std_logic_vector(2 downto 0);
a2 : in std_logic_vector(2 downto 0);
a3 : in std_logic_vector(2 downto 0);
a4 : in std_logic_vector(2 downto 0);
sel : in std_logic_vector(1 downto 0);
b : out std_logic_vector(2 downto 0)
);
end mux4;
architecture rtl of mux4 is
-- declarative part: empty
begin
p_mux : process(a1,a2,a3,a4,sel)
begin
case sel is
when "00" => b <= a1 ;
when "01" => b <= a2 ;
when "10" => b <= a3 ;
when others => b <= a4 ;
end case;
end process p_mux;
end rtl;
[3] The D-type flip-flop samples an incoming signal at the rising (or falling) edge of a clock.
This example has an asynchronous, active-high reset, and samples at the rising clock
edge.
DFF : process(all) is
begin
if RST then
Q <= '0';
elsif rising_edge(CLK) then
Q <= D;
end if;
end process DFF;
[4] The following example is an up-counter with asynchronous reset, parallel load and
configurable width. It demonstrates the use of the 'unsigned' type, type conversions
between 'unsigned' and 'std_logic_vector' and VHDL generics. The generics are very close
to arguments or templates in other traditional programming languages like C++. The
example is in VHDL 2008 language.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type
entity COUNTER is
generic (
WIDTH : in natural := 32);
port (
RST : in std_logic;
CLK : in std_logic;
LOAD : in std_logic;
DATA : in std_logic_vector(WIDTH-1 downto 0);
Q : out std_logic_vector(WIDTH-1 downto 0));
end entity COUNTER;
architecture RTL of COUNTER is
begin
process(all) is
begin
if RST then
Q <= (others => '0');
elsif rising_edge(CLK) then
if LOAD='1' then
Q <= DATA;
else
Q <= std_logic_vector(unsigned(Q) + 1);
end if;
end if;
end process;
end architecture RTL;
