6/28/22, 8:27 PM Routing ~ VLSI Guide
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Routing
VLSI Guide 23:17 Physical Design Flow 10 comments
Definition
Routing is the stage after CTS where the interconnections are made by
determining the precise paths for each nets.
This includes the interconnection of the standard cells, the macro pins, the pins
of the block boundary or the pads of the chip boundary.
After CTS, the tool will be having the information about the exact locations of
the standard cells, the pins, the IO ports and the pads.
The logical connectivity is defined by the netlist and the design rules are defined
in the technology file are available to the tool. In routing stage, metal and vias
are used to create the electrical connection in layout so as to complete all
connections defined by the netlist.
So in short, routing can be termed as allocating set of wires in the routing space
that connects all the nets in the netlist by using certain design rules for the
metals and vias used in doing so.
Goals of Routing
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Establishing the entire connectivity of the design with minimum number of vias
and optimized total wire length.
To meet the timing constraints.
No LVS errors (Layout vs Schematic) ie, the all the connections described in the
netlist are completed physically.
No DRC (Design Rules Check) violations in doing so.
Complete routing within the area of the design.
Inputs
Design which is done with placement, CTS and optimization.
Output
Design with completed interconnection and geometric layout of the nets.
Prerequisites and Checks
Timing DRC and QoR post CTS must be acceptable.
Acceptable global routing congestion.
HFNS should be less than the specified limit.
Check for overlapping cells, if any.
Check for any blocked pins, ports or PG connection.
Stages of Routing
Global Routing.
Track Assignment.
Detailed Routing.
Search and Repair.
Each stages of routing are described below.
1. Global Routing
In global routing, the region to be routed are divided into
sectors(tiles/rectangles) called global routing cells or gcells.
Then it decides tile to tile path for the nets and simultaneously trying to
optimize the length, without actually making any physical connection.
The routing capacity of each gcell depends on the blockages, routing tracks, pin
density inside it.
This rough routing is done on the basis of available tracks in the region.
If the required routing resources are greater than the available routing resources,
then it will lead to congestion.
So it is called coarse grain routing assignment.
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Objectives of global routing
Minimize total overflow.
Minimize total wire length.
Minimize total run time for carrying out routing process.
2. Track Assignment
After the gcell estimation, tracks are assigned to each global routes.
The tracks are assigned in vertical and horizontal direction for each partition.
The direction of routing is dependent on the metal used, which has preferred
routing direction. For eg. If Metal 1 has routing direction Horizontal, then Metal
2 has direction Vertical.
In this stage, the global routes are replaced with metal layers, which has many
DRC violations, Signal Integrity (SI) and timing violations.
3. Detailed Routing
In detailed routing, the router uses the scheme made in the global routing and
track assignment phases to lay metals to connect the nets to the pins.
The violations that were created in the previous stage, will be fixed by multiple
iterations of routing, so that no connections will be left short , open or spacing
violations.
First, the block is divided into specific areas called the Sboxes (switch boxes)
which comprises of multiple gcells.
These boxes are in alignment with the gcell boundary.
4. Search and Repair
It is done along with detailed routing, specifically after the primary iteration.
The shorts and spacing violations are sorted and is fixed.
Fill Stage
Fill stage comes after routing optimization, where filler cells and metal fills are added to
meet the DRC rules. Two steps are mainly performed in this stage.
1. Adding Filler Cells
2. Adding Metal Fills
Adding Filler Cells
Filler cells are used for rail continuity and to fill up gaps between standard cells
in the rows, and thereby reducing the DRC violations created by the base layers.
Filler cells are physical-only cells designed in such a way that they contain only
n-well, p-well & power rails.
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It is also possible to reduce the IR drop by inserting de-cap filler cells, but this
comes at a cost of higher leakage currents.
Adding Metal Fills
The metal fills also known as dummy metal layers, are small, floating metal nets,
inserted in empty spaces in the design after post-route optimization in order to
maintain uniformity in metal layer density.
These are added to meet the metal density DRC rules (density violations) which
are mandatory by most manufacturing processes.
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10 comments:
Rama murthy 10 May 2019 at 23:37
Thanks Great work please upload new topics we are waiting
Reply
Unknown 4 August 2019 at 12:54
Great information... Thanks Sir
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Reply
Anonymous 7 August 2019 at 22:46
Good outline...Nice
Reply
Hem 9 September 2019 at 23:36
Great notes
Reply
Hem 9 September 2019 at 23:37
Please write on data and clock Tran fixes, double switching etc
Reply
Hem 9 September 2019 at 23:37
Also please write on ECO flow
Reply
Anonymous 11 November 2019 at 07:50
What are the checks done after routing? Can u tell me sir
Reply
Anonymous 21 August 2020 at 15:20
How do I remove the blocked ports issue I'm facing before going to routing?
Reply
KITS Technologies 30 September 2021 at 14:03
SAP Secrity and sap grc online training
Reply
Unknown 8 February 2022 at 17:58
Very useful notes
Thank uh
Reply
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