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Verilog Part2

The document describes three different models - structural, behavioral, and data flow - for implementing a full adder circuit in Verilog. The structural model uses half adders as sub-modules, the behavioral model describes logic functions using always blocks, and the data flow model uses assign statements to describe signal flow. Each model is tested by simulating input patterns and monitoring the output sum and carry signals.

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Tasneem A
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20 views4 pages

Verilog Part2

The document describes three different models - structural, behavioral, and data flow - for implementing a full adder circuit in Verilog. The structural model uses half adders as sub-modules, the behavioral model describes logic functions using always blocks, and the data flow model uses assign statements to describe signal flow. Each model is tested by simulating input patterns and monitoring the output sum and carry signals.

Uploaded by

Tasneem A
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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//FULL ADDER-STRUCTURAL MODEL


-----------------------------------------------------------------------------------------
module FULL_ADDER;
reg a,b,c;
wire sum1,cout;
fa f1(.a(a), .b(b), .c(c), .S(S), .Cout(Cout));
initial begin
#0 a=0; b=0; c=0;
#20 a=0; b=0; c=1;
#30 a=0; b=1; c=0;
#40 a=0; b=1; c=1;
#50 a=1; b=0; c=0;
#60 a=1; b=0; c=1;
#70 a=1; b=1; c=0;
#80 a=1; b=1; c=1;
end
initial begin
$display("Full adder using Half adder in structural model");
$monitor("a=%b b=%b c=%b sum=%b cout=%b", a,b,c,S,Cout);
end
endmodule
module ha(a,b,S,Cout);
input a,b;
output S, Cout;
xor(S,a,b);
and(Cout,a,b);
endmodule
module fa(a,b,c,S,Cout);
input a,b,c;
output S, Cout;
wire S1,C1,C2;
ha h1(.a(a), .b(b), .S(S1), .Cout(C1));
ha h2(.a(S1), .b(c), .S(S), . Cout(C2));
or(Cout, C1, C2);
endmodule
-----------------------------------------------------------------------------------------
//FULL ADDER-BEHAVIORAL MODEL
-----------------------------------------------------------------------------------------
module Full_adder;
reg a,b,c;
wire S,Cout;
fa f1(.a(a), .b(b), .c(c), .S(S), .Cout(Cout));
initial begin
#0 a=0; b=0; c=0;
#20 a=0; b=0; c=1;
#20 a=0; b=1; c=0;
#20 a=0; b=1; c=1;
#20 a=1; b=0; c=0;
#20 a=1; b=0; c=1;
#20 a=1; b=1; c=0;
#20 a=1; b=1; c=1;
end
initial begin
$monitor("a=%b b=%b C=%b sum=%b cout=%b", a,b,c,S,Cout);
end
endmodule
module ha(a,b,S,Cout);
input a,b;
output S, Cout;
reg S, Cout;
always @(a,b) begin
S=a ^ b;
Cout=a&b;
end
endmodule
module fa(a,b,c,S,Cout);
input a,b,c;
output S, Cout;
wire S1,C1,C2;
reg Cout;
ha h1(.a(a), .b(b), .S(S1), .Cout(C1));
ha h2(.a(S1), .b(c), .S(S), .Cout(C2));
always @(C1,C2) begin
Cout=C1 | C2;
end
endmodule

-----------------------------------------------------------------------------------------
//FULL ADDER-DATA FLOW MODEL
-----------------------------------------------------------------------------------------
module FULL_ADDER;
reg a,b,c;
wire sum1,cout;
fa f1(.a(a), .b(b), .c(c), .S(S), .Cout(Cout));
initial begin
#0 a=0; b=0; c=0;
#20 a=0; b=0; c=1;
#30 a=0; b=1; c=0;
#40 a=0; b=1; c=1;
#50 a=1; b=0; c=0;
#60 a=1; b=0; c=1;
#70 a=1; b=1; c=0;
#80 a=1; b=1; c=1;
end
initial begin
$monitor("a=%b b=%b c=%b sum=%b cout=%b", a,b,c,S,Cout);
end
endmodule
module fa(a,b,c,S,Cout);
input a,b,c;
output S, Cout;
wire S1,C1,C2;
ha h1(.a(a), .b(b), .S(S1), .Cout(C1));
ha h2(.a(S1), .b(c), .S(S), . Cout(C2));
assign Cout=C1 | C2;
endmodule
module ha(a,b,S,Cout);
input a,b;
output S, Cout;
assign S=a^b;
assign Cout=a&b;
endmodule

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