module AND_Gate (
output Y,
input A,
input B
);
assign Y=A&B;
endmodule
-------------------------------------------------------------------------------------------------------
Module OR_Gate (
output y,
input A,
input B
);
Assign Y=A|B;
endmodule
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module XOR_Gate (
output Y,
input A,
input B
);
assign Y = A ^ B;
Endmodule
module NOT_Gate (
output Y,
input A
);
assign Y = ~A;
endmodule
-------------------------------------------------------------------------------------------------------
module Basic_Gates (
input [3:0] A,
input [3:0] B,
output [3:0] and_out,
output [3:0] or_out,
output [3:0] xor_out,
output [3:0] not_out
);
AND_Gate and0 (and_out[0], A[0], B[0]);
AND_Gate and1 (and_out[1], A[1], B[1]);
AND_Gate and2 (and_out[2], A[2], B[2]);
AND_Gate and3 (and_out[3], A[3], B[3]);
OR_Gate or0 (or_out[0], A[0], B[0]);
OR_Gate or1 (or_out[1], A[1], B[1]);
OR_Gate or2 (or_out[2], A[2], B[2]);
OR_Gate or3 (or_out[3], A[3], B[3]);
XOR_Gate xor0 (xor_out[0], A[0], B[0]);
XOR_Gate xor1 (xor_out[1], A[1], B[1]);
XOR_Gate xor2 (xor_out[2], A[2], B[2]);
XOR_Gate xor3 (xor_out[3], A[3], B[3]);
NOT_Gate not0 (not_out[0], A[0]);
NOT_Gate not1 (not_out[1], A[1]);
NOT_Gate not2 (not_out[2], A[2]);
NOT_Gate not3 (not_out[3], A[3]);
endmodule
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module Full_Adder (
input A,
input B,
input Cin,
output Sum,
output Cout
);
wire AB_xor;
wire A_and_B;
wire Cin_and_AB;
xor U1 (AB_xor, A, B);
xor U2 (Sum, AB_xor, Cin);
and U3 (A_and_B, A, B);
and U4 (Cin_and_AB, Cin, AB_xor);
or U5 (Cout, A_and_B, Cin_and_AB);
endmodule
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module Add_Sub (
output [3:0] Sum,
output C,
input [3:0] A, B,
input Sub
);
wire [3:0] B_eff;
// Compute the effective value of B based on the Sub signal
assign B_eff = B ^ (4'b0001 << Sub);
// Perform addition or subtraction
assign {C, Sum} = A + B_eff + Sub;
endmodule
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module MUX_5tol (
input [3:0] in0,
input [3:0] inl,
input [3:0] in2,
input [3:0] in3,
input [3:0] in4,
input [2:0] Opcode,
output reg [3:0] Out
);
always @(*) begin
case (Opcode)
3'b000: Out = in0;
3'b001: Out = inl;
3'b010: Out = in2;
3'b011: Out = in3;
3'b100: Out = in4;
default: Out = 4'b0000;
endcase
end
Endmodule
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Module ALU_dbit (
Input [3:0] A,
Input [3:0] B,
Input [2:0] Opcode,
Output reg [3:0] Out,
Output reg C,
Output reg Z,
Output reg sign_bit
);
Wire [3:0] and_out, or_out, xor_out, not_out;
AND_Gate and1 (and_out([0], A[0], B[O]):
AND Gate and2 (and_out(l], A[l], B[l]):
AND_Gate and3 (and out(2], A[2], B[2]):
AND Gate and4 (and_out([3], A[3], B[3]):
OR_Gate or1 (or_out([0], A[0], B[0]
OR_Gate or2 (or_out[l], A[l], B[l]):
OR Gate or3 (or_out([2], A[2], B[2]):
OR_Gate or4 (or_out[3], A[3], B[3]):
XOR_Gate xor1 (xor_out([0], A[0], B[0]):
XOR_Gate xor2 (xor_out(l], A[l], B[1]):
XOR_Gate xor3 (xor_out([2], A[2], B[2]):
XOR_Gate xor4 (xor_out[3], A[3], B[3]):
NOT_Gate not1 (not_out([0], A[0]):
NOT_Gate not2 (not_out(l], A[l]);
NOT_Gate not3 (not_out(2], A[2]):
NOT_Gate not4 (not_out[3], A[3]):
Reg [4:0] sum1;
Reg [4:0] sum;
Reg [3:0] B_twos_complement;
Always @(*)
Begin
Out <= 4’b0000;
Sign_bit <= 0;
Case (Opcode)
3’b000; begin
{C, Out} <= A+B;
End
3’b001: begin
C <= 0;
If (A < B) begin
B_twos_complement <= ~ B +1;
Sum1 <= A+B_twos_complement;
Sum <= sum1 + 1;
out <= sum[3 :0;
Sign_bit <= 1;
End else begin
Out <= A - B;
Sign_bit <= 0;
End
End
3’b010: begin
Out <= and_out;
C <= 0;
End
3’b011: begin
Out <= or_out;
C <= 0;
End
3’b100: begin
Out <= xor_out;
C <= 0;
End
3’b010: begin
Out <= not_out;
C <= 0;
End
default: begin
Out <= 4’b0000;
C <= 0;
End
endcase
Z <= (Out == 4’b0000) ? 1’b1 : 1’b0;
End
Endmodul
