2022 SCHEME VERILOG PROGRAMS (VLSI LAB)

Module dff(d,clk,rst,q,qb); module dff_tb();

input d,clk,rst; reg d,clk,rst;
output q,qb; wire q,qb;
reg q; dff dff_tb(d,clk,rst,q,qb);
always@(posedge clk) initial
begin begin
if(rst) clk=0;
q<=1'b0; forever#5 clk=~clk;
else end
q<=d; initial
end begin
assign qb=~q; #10 rst=0;
endmodule #10 rst=1;
#10 rst=0;
#10 rst=1;
end
initial
begin
d=0;
#15 d=1;
#15 d=0;
#15 d=1;
#30 d=0;
#300 $finish;
end
endmodule

module srff(s,r,clk,q,q1); module srff_tb();

input s,r,clk; reg s,r,clk;
output reg q,q1; wire q,q1;
initial srff
begin srff_tb(.s(s),.r(r),.clk(clk),.q(q),.q1(q1));
q=0; initial
q1=1; clk=0;
end always
always@ (posedge clk) #10 clk=~clk;
begin initial
case({s,r}) begin
2'b00:q=q; s=0;r=0;
2'b01:q=0; #100 s=0;r=0;
2'b10:q=1; #100 s=1;r=0;
2'b11:q=1'bx; #100 s=1;r=1;
endcase #100 s=0;r=1;
q1=~q; #300 $finish;
end end
endmodule endmodule
module jkff module jkff_tb;
(j,k,clk,rst,q,qb); reg j,k,clk,rst=1;
input j,k,clk,rst; wire q,qb;
output q,qb; jkff
reg q; jkff_tb(.clk(clk),.rst(rst),.j(j),.k(k),.q(q),.qb(qb));
wire j,k,clk,rst,qb; always #10 clk = ~clk;
always@(posedge clk) initial
begin begin
if(rst==1) clk=0;
q<=1'b0; rst=1;
else if(j==0 && k==0) j=0;
q<=q; k=0;
else if(j==0 && k==1) #30
q<=1'b0; j <= 0;
else if(j==1 && k==0) k <= 0;
q<=1'b1; rst=0;
else if(j==1 && k==1) #30 j <= 0;
q<=~q; k <= 1;
end #30 j <= 1;
assign qb=~q; k <= 0;
endmodule #30 j <= 1;
k <= 1;
#200 $finish;
end
endmodule

module four_bit_adder module four_bit_adder_tb;

(input [3:0] a,input reg [3:0] a, b;
[3:0] b,input reg cin;
cin,output [3:0] wire [3:0] sum;
sum,output cout); wire cout;
assign {cout, sum} = a four_bit_adder four_bit_adder_tb
+ b + cin; (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
endmodule initial
begin
a = 4'b0000; b = 4'b0000; cin = 0; #10;
a = 4'b0011; b = 4'b0101; cin = 0; #10;
a = 4'b1111; b = 4'b0001; cin = 0; #10;
a = 4'b1010; b = 4'b0101; cin = 1; #10;
a = 4'b1111; b = 4'b1111; cin = 1; #10;
#300 $finish;
end
endmodule
module four_bit_multiplier (input module four_bit_multiplier_tb;
[3:0] a,input [3:0] b,output [7:0] reg [3:0] a, b;
product); wire [7:0] product;
reg [7:0] temp_product; four_bit_multiplier
integer i; four_bit_multiplier_tb
always @(*) (.a(a),.b(b),.product(product));
begin initial
temp_product = 0; begin
for(i=0;i<4;i=i+1) a = 4'b0000; b = 4'b0000; #10;
begin a = 4'b0011; b = 4'b0010; #10;
if (b[i]) a = 4'b1111; b = 4'b0001; #10;
temp_product = temp_product + (a a = 4'b0010; b = 4'b0100; #10;
<< i); a = 4'b1111; b = 4'b1111; #10;
end $finish;
end end
assign product = temp_product; endmodule
endmodule

module mod_n_counter module mod_n_counter_tb;

#(parameter N=10,parameter parameter N=10;
WIDTH=4) parameter WIDTH=4;
(input clk,input rstn,output reg clk;
reg[WIDTH-1:0] out); reg rstn;
always@(posedge clk) wire [WIDTH-1:0] out;
begin mod_n_counter mod_n_counter_tb
if(!rstn) (.clk(clk),.rstn(rstn),.out(out));
begin always #10 clk=~clk;
out<=0; initial
end begin
else {clk, rstn}<=0;
begin repeat(2)@ (posedge clk);
if(out==N-1) rstn<=1;
out<=0; repeat(20)@ (posedge clk);
else $finish;
out<=out+1; end
end endmodule
end
endmodule
module alu(a,b,c,y); module alu_tb();
input[31:0]a; reg [31:0]a;
input[31:0]b; reg [31:0]b;
input[2:0]c; reg [2:0]c;
output reg[31:0]y; wire [31:0]y;
always@(*) alu alu_tb(a,b,c,y);
begin initial
if (c==3'b000) begin
y=a&b; a=32'b00000000;
else if (c==3'b001) b=32'b01010101;
y=a/b; c=3'b000;
else if (c==3'b010) #10 c=3'b001;
y=a^b; #10 c=3'b010;
else if (c==3'b011) #10 c=3'b011;
y=~(a&b); #10 c=3'b100;
else if (c==3'b100) #10 c=3'b101;
y=a+b; #10 c=3'b110;
else if (c==3'b101) #10 c=3'b111;
y=a-b; #10 c=3'bxxx;
else if (c==3'b110) end
y=a*b; initial
else if (c==3'b111) begin
y=a%b; #100 $finish;
else end
y=32'bxxx; endmodule
end
endmodule