LOGIC II COURSE
Lecture 1
Introduction to Basic
Digital Logic
Dr. Marwa Gamal
What does “Digital” mean?
Represented by discrete (stepped)
or numerical values rather than
analog (continuous) values.
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Advantages of Digital Systems/Values
Relatively less sensitive to distortion (noise and losses)
Can be reproduced more accurately
Easier to reconstruct a signal
More storage and transfer options
Can be processed mathematically and logically
Systems are easier to design electrically (fewer voltage
/current issues)
Digital systems can be made small (low current)
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Disadvantages of digital systems/values
Takes time to convert and process values
Can become quite complex with an increase
of significant digits
Often need to convert to / from analog
systems
More sensitive to environmental issues
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Number Systems
Decimal numbering system
•Decimal values are difficult to represent in
electrical systems. Ex: 23 10
Binary Signals
Binary Signals have two basic states:
1(logic “high”, or H, or “on”, or “True”)
0 (logic “low”, or L, or “off”, or “False”)
Ex: 01110012
Hexadecimal
is used to simplify dealing with large binary values
Ex: A6C316
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Basic Digital Logic Functions
3 primary functions (the Basic Gates):
AND
OR
NOT
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Inputs Output
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Timing diagrams for AND gate
Timing diagrams are the best means of
comparing the input and output logic values of a
digital circuit over time, such as would be found in
a functioning circuit.
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Inputs Output
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Inputs Output
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Combinational logic circuits can be
described with:
English Terms
Boolean equations
Truth Tables
Logic diagrams
Timing Diagrams
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Combinational logic circuits
NAND gate (NOT gate +AND gate.)
NOR gate (NOT gate +OR gate)
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X-OR X-NOR
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Combinational logic vs. Sequential logic
circuits
Combinational Logic:
Output depends only on current input
Able to perform useful operations (add/subtract/multiply/…)
Has no memory
Sequential Logic:
Output depends not only on current input but also on past input
values, e.g., design a counter
Need some type of memory to remember the past input values
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•Combines combinational logic gates with memory devices.
•Accepts logic signals from external inputs and from the
outputs of the memory elements.
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Synchronous vs. Asynchronous
There are two types of sequential circuits:
Synchronous sequential circuit: circuit output
changes only at some discrete instants of time. This
type of circuits achieves synchronization by using a
timing signal called the clock.
Asynchronous sequential circuit: circuit output can
change at any time (clockless).
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Synchronous Sequential Circuits:
Flip flops as state memory
The most important memory element is the flip-flop (FF).
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Flip-flops
The flip-flop is known by other names, including latch and
bistable multivibrator
The most basic FF circuit can be constructed from either
two NAND gates or two NOR gates (SR latch). logicII
NAND GATE LATCH
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SR Latch (NAND version)
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
X Y NAND
00 1
01 1
10 1
11 0
SR Latch (NAND version)
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
SR Latch (NAND version)
0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
NOR GATE LATCH
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Clocked Flip-Flop
It is activated by a signal transition; this is indicated
by the presence of a small triangle on the CLK
input.
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Clocked J-K FLIP-FLOP
• Operates like the S-R FF.
• J is set, K is clear.
• When J and K are both high the output is
toggled from whatever state it is in to the
opposite state.
• May be positive going or negative going clock
trigger.
• Has the ability to do everything the S-R FF
does, plus operate in toggle mode.
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Clocked J-K FLIP-FLOP
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Clocked D FLIP-FLOP
One data input.
The output changes to the value of the input at
either the positive going or negative going clock
trigger.
May be implemented with a J-K FF by tying the J
input to the K input through an inverter.
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Implementation of the D FLIP-FLOP
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Transparent D Latch
• One data input.
• The clock has been replaced by an enable line.
• The output follows the input only when EN is
high.
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Preset-Clear Flip-flop
D FLIP-FLOP with Asynchronous Inputs
•The labels PRE and CLR are used for asynchronous inputs.
• Active low asynchronous inputs will have a bar over the
labels and inversion bubbles.
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Preset-Clear Flip-flop
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Lecture 1 finished
Thanks
