EMT 5206: PROGRAMMABLE LOGIC

CONTROLLERS AND THEIR

APPLICATIONS

LECTURE NOTES (5)

FLIP-FLOPS
January-April 2019
 Summary
• To discuss the difference between combinational and sequential
logic as well as the difference between asynchronous and
synchronous circuits and to show why the operation of synchronous
circuits is more predictable, given propagation delays.
• To explain the operation of the common latches and flip-flops
– SR or set–reset latch, which may also be called a SR flip-flop
– D or data flip-flop
– T or toggle flip-flop
– JK flip-flop
• To describe clocking and the differences between positive edge and
negative edge triggering and discuss the type of control inputs —
active high and active low; asynchronous, jam or direct.
 Combinational Logic
• The outputs depend only on the state of the inputs all of the time.
Any change in the state of one of the inputs will ripple through the
circuit immediately.
o Examples of combinational logic are NAND and NOR gates,
Inverters, and Buffers. These four logic gates form the basis of
almost all combinational logic circuits as well as flip flops.
• Circuits that change the state of the output in this manner are also
known as asynchronous circuits.
o However, not all asynchronous circuits are combinational logic
circuits.
 Sequential Logic
• Has memory; the circuit stores the result of the previous set of
inputs. The current output depends on inputs in the past as well as
present inputs.
o The basic element in sequential logic is the bistable latch or flip-
flop, which acts as a memory element for one bit of data.
 Clocked Circuits
•Most flip-flops are clocked so that the output change state
based upon the state of the inputs at precisely determined
times.
o Usage varies — in this course, ‘flip-flops’ will be used for clocked
circuits and ‘latches’ for circuits that are asynchronous.

• A common clock used in many flip-flops in one circuit ensures

that all parts of a digital system change state at the same
time. This is called a synchronous system
 Bistable Circuit
• At the heart of a bistable circuit is a pair of inverters connected in a
loop — with feedback, in other words. It has two stable states.
– Without some control, there isn’t a way to force the bistable
circuit into one or the other state.
 Bistable Circuits
• The bistable circuit is used as a ‘bus keeper’ to hold a node at a
definite 1 or 0. It is also the heart of a ‘static random-access memory’
(SRAM) cell.
o Similar operation occurs for any ring composed of an even number
of inverters.
o What would happen if 3 inverters (or larger odd number) are
connected in series?
❑ This type of circuit is called a ring oscillator.
❑ Check this out in the laboratory or in PSpice!
Core of a Flip-Flop: The set–reset or SR
Latch
• Acts as a simple memory with two stable states at the two output
when S = R = 0

– Q1 and Q2 are the outputs of the S-R latch.

– When Q1 is known as Q and Q2 is also called Q’ or Q (spoken
as Q bar), meaning that its value is not Q or the opposite of Q.
 S-R Latch
Acts as a simple memory with two stable states when S =
R = 0:

• The latch
- holds (stores) when S = R = 0
- is set (to 1) by bringing S = 1 with R = 0
- is reset (to 0) or cleared by bringing R = 1 with S = 0
• The condition S = R = 1 must be avoided because it leads to an
indeterminate condition, where the output can not be predicted at
any one point in time. This can cause a race condition to occur when
the inputs change to S = R = 0.
 SR Latch with Enable

• The S and R inputs only effect the output states when the enable input C
is high.
– This controls when the latch responds to its inputs.
• The latch holds (stores) its value while the enable input is low — latches
it!
• Any changes in the inputs during the time when enable is high will
affect the output immediately: the circuit is said to be transparent.
• This circuit still has a major problem: the stored value is
indeterminate if S = R = 1 when the clock goes low
 Logic Table
SR Latch SR Latch with Enable

S R Q S R E Q
0 0 Last Q 0 0 1 Last Q
0 1 0 0 1 1 0
1 0 1 1 0 1 1
1 1 1 1 1
X X 0 Last Q
Timing Diagram
 Timing Diagram
No Initial Condition Indeterminate Condition, Q = Q’
Propagation Delay Time Followed by a Race Condition
 Task
• The two NAND gates form a SR latch.
– SR latches can be made using OR, NOR, or AND gates. Can you
design one and work out the logic table for its operation?
• Depending on the design and which output is called Q, the
race condition occurs when S = R = 0 and the last Q state
occurs when S = R = 1.
– Can you predict the logic table before you have
constructed the circuit and simulated/measured output
for the four sets of input states?
 74279
Note that there is dual SR bar latch in PSpice (2 in 1 part).
It may appear that the undefined operation has been
designed out of its operation when you use this part in
a simulation. However, the datasheet indicates that
the race condition may show up.
 D Flip-Flop

S=R
The problem with S = R = 1 can be avoided using a common input D as shown
above so that .
The output of the latch now:
follows the D input while C = 1 (transparent)
holds its value while C = 0 (Q = last Q when C went low) no matter what
happens at the input
This circuit is often called a transparent latch. It can be bought as an
integrated circuit, usually with several latches in a package.
The input C may be called control, clock, gate, or enable.
 Timing Diagrams
D D Q
output remains constant:
C output follows input input ‘latched’ C

Q
Q

D D Q
output remains constant:
C' output follows input input ‘latched’ C

Q
Q
 Transparent Latches
• Transparent latches have important applications in digital
electronics.
– However, the stability of the output can be an issue in noisy
environments.
– It is more convenient if the behaviour depends on the inputs
only at a particular time, which led to the invention of edge-
triggered flip-flops.
• Transparent latches are sometimes called ‘level-sensitive’
flip-flops to distinguish them from edge-sensitive devices.
Yet another name is ‘half flip-flop’.
 Edge-Triggered Flip-Flops
These circuits respond to their inputs on either the rising or falling edge of
the clock — a precise point in time rather than an interval.

Positive edge triggered Negative edge triggered

rising edge of clock falling edge of clock

D Q D Q
additional of a circle
wedge shows positive
means that there is
edge triggering
negative edge triggering

Older flip-flops may be ‘pulse-triggered’, which require a clock pulse that

goes from 0→1→0 or a ‘master–slave’ types but these are now obsolete.
 Excitation Tables
Logic tables show the state of the output(s) of a logic circuit as a function of its
inputs at the same time.

Since, clocked digital systems have memory, their behaviour depends on inputs in
the past as well as the present values of the inputs.
Thus, flip-flops cannot be described by simple truth tables. Instead, we use
excitation or transition tables. These show:
•output before the clock transition — often labelled Qn
•inputs at the clock transition — such as S and R

•occasionally the type of clock transition – positive/negative edge-triggered

•the resulting output after the clock transition — often labelled Qn+1
It is important to remember that Qn and Qn+1 describe the same signal but at
different times. The notation can vary, e.g. Q0 and Q instead.
 D Flip-Flop
D C Qn Qn+1 description D Q
0 0 0
Clear
0 1 0 (reset)
1 0 1 Q
Set
1 1 1
input output output
at before after Qn+1 = D
clock clock clock

A D flip-flop simply stores the value on its D input at the clock transition. The
previous value stored, Qn, has no effect, unlike other flip-flops.
It therefore acts as a simple memory or ‘latch’. The most widely used flip-
flops: simple to build and design with. A register comprises several D flip-
flops, one for each bit to be stored.
 Timing Diagram: Edge-Triggered FF

D Q
C

D Q

The input D can change at any time because it comes from other parts of the
system — it is not necessarily synchronized to the clock (it may be from a
switch on the front panel, for instance). However, the flip-flop only changes
its output when the clock pulse rises.
 Toggle (T) Flip-Flop
T Q
T Qn Qn+1 description

0 0 0
hold
0 1 1
1 0 1
Q
toggle
1 1 0

Qn+1 = T ≈ Qn = T ◊Qn + T ◊Qn

Note that the output depends on the previous value stored, Qn. This type of
flip-flop is rarely bought as a ‘dedicated’ device — you can easily make a T
from a D flip-flop. Aside: it is not possible to put a specific value into a T flip-
flop – it can only toggle or hold.
 What does this circuit do?

Assume that the initial state of Q0, Q1, Q2, and Q3 are all logical zeros.
1. Determine how Q0 changes as the clock pulse goes from 0 →1 →0 →1.
2. After how many clock pulses will Q1 change state from ‘0’ to ‘1’?
3. After how many clock pulses will Q2 change state from ‘0’ to ‘1’?
4. After how many clock pulses will Q3 change state from ‘0’ to ‘1’?
 S-R Latch
S R C Qn Qn+1 description
S Q
0 0 0 0 hold
0 0 1 1 C
0 1 0 0 clear (reset)
0 1 1 0 R Q
1 0 0 1 set
1 0 1 1
1 1 0 ? indeterminate
1 1 1 ? — avoid

inputs output output

at before after
clock transition clock clock
 JK Flip-Flop
J K Qn Qn+1 description
J Q
0 0 0 0 hold
0 0 1 1
0 1 0 0 clear (reset)
0 1 1 0
K Q
1 0 0 1 set
1 0 1 1 Qn+1 = J ◊ Qn + K ◊ Qn
1 1 0 1 toggle
1 1 1 0

The excitation table for a JK flip-flop is similar to SR flip-flop but doesn’t have the
problem of S = R = 1. It can perform all the operations of the simpler types of flip-
flop. However, the design of the circuit internal to the flip-flop makes it more
expensive to manufacture than a number of other flip-flops so JK flip-flops are now
rarely used.
 Timing Diagram: JK Flip-Flop
C

hold set hold clear toggle set

(no effect)
Suggestion: Determine the Q output for a negative edge triggered JK flip-
flop with the inputs shown above, assuming that Q starts at logic 0.
Same Operation as Circuit on pervious
Slide

Task: Prove this to yourself.

 Control Pins
Flip-flops and more complicated circuits often have inputs, such as clear,
preset, enable, and load. The state of the control pins has priority of the D and
Clock inputs when determining the state of the output.

• Clear (CLR) resets the flip-flop output to 0 — the most common control input
• Preset (PRE) sets the flip-flop output to 1
More complicated circuits such as counters may have additional control inputs for
up/down, count/hold, load, etc. Microprocessors usually have a reset pin.
 Active Low Controls
Control inputs are often active low, shown by a bar over the label
or a circle for negation (or both as in the component below).

Active low inputs should be:

• kept high for normal operation
• changed to low to preset or clear the device.

The reason for making these active low is historical. Check the data
sheet to be sure!
 Asynchronous Control
Another feature of control inputs is that they are often asynchronous. This
means that they take effect immediately and do not wait for a clock
transition.

Compare
• D takes effect only at a clock transition (positive edge)
• clear and preset act immediately to ‘overrule’ D

Asynchronous inputs are sometimes called direct or jam inputs.

Always check the data sheet because some control inputs are synchronous!
 Propagation Delay
We have seen that most modern logic devices are triggered on either the
rising or falling edge of the clock. The output does not respond instantly,
but only after a time called the propagation delay, tpd.
Here is an example for a D flip-flop that was measured in a lab.

74HC74
flip-flop at 3 V
propagation
delay, tpd
(about 16 ns)
 Limitations on Circuit: tpd
The propagation delay is important for several reasons:

•It limits the speed at which circuits can be clocked (20 or 30 MHz for the
‘HC’ family of components, used in the laboratory)
•Signals that pass through different numbers of components receive
different delays, as in a ripple counter. Time must be allowed for all outputs
to settle down before the system attempts to change state again.
•The delay helps to keep digital circuits with feedback stable (this applies to
virtually all practical circuits).
- Each logic gate responds to its at the clock transition.
- Because of tpd, the outputs change after the propagation delay.
- This affects the inputs that are connected to outputs.
- However, these gates are no longer acting on their inputs until the next
clock transition arrives.
 Would this circuit work?
What would happen if tpd is longer than the period of the clock?
What would happen if tpd is about equal to the clock’s period?

LET’S KEEP LEARNING…………………………..