Table 3.
5 Default register assignments
A typical application for the segment override is to allow data to be stored in the code
segment.
Example 3.4
CODE SEGMENT
COUNT DB 0FFH
MOV AL, CS:COUNT
The variable COUNT is defined within the code segment, requiring the MOV instruction
to use the CS: override to access this memory location.
3.6 STRING INSTRUCTION
These instructions are used for moving large blocks of data or strings. For all these
instructions the memory source is DS:SI and the memory destination is ES:DI. Segment
override can applied only to the source address. The destination must be the extra
segment. The offset memory pointers, DI and SI, are automatically incremented or
decremented depending on the state of DF by 1 for bytes or by 2 for words.
STOS (store string byte or word) and LODS (load string byte or word) instructions
transfer a byte or word from the accumulator to memory or from the memory to the
accumulator
MOVS (move string byte or word) instruction combines these two operations,
transferring the byte or word from the memory source to the memory destination.
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Table 3.6 segment override prefix
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Table 3.7 string instruction
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SCAS (scan string byte or word) and CMPS (compare string byte or word) instructions
allow the destination byte or word to be compared with the accumulator (SCAS) or the
memory source (CMPS). After execution the flags are set to reflect the relationship of the
destination to the source element. The conditional jump instructions can then be used to
make decision such as “jump if AL is greater than the memory byte” or “jump if the
destination memory word equals the source memory word.”
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3.7 REPEAT PREFIX
Preceding the instructions STOS or MOVS with the REP (repeat) instruction causes these
instructions to be repeated a number of times equal to the contents of the CX register. By
loading CX with the number of words or bytes to be moved, a single string instruction
(and REP prefix) can move up to 65,536 bytes.
Table 3.8 repeat prefix
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Example 3.5
Write the 8086 program required to fill the 1000D byte of memory in the extra segment
beginning at address BLOCK with the data byte 20H. Assumed that the DF is to be 0.
Solution
MOV AL, 20H ;AL holds the data byte
LEA DI, BLOCK ;DI holds the address of block
MOV CX, 03E7H ;load CX with 1000D
REP STOSB ;store AL at ES:DI, increment
;DI, and repeat 1000 times
REPE/REPZ (repeat while equal or zero) and REPNE/REPNZ (repeat while not equal
or not zero) forms of the REP prefix are intended for use with the SCAS and CMPS
string instructions. They allow the string operation to be repeated while equal
(REPE/REPZ) or while not equal (REPNE/REPNZ).
3.8 LOGICAL INSTRUCTIONS
The logical instructions refers to the Boolean logical functions, such as AND, OR, NOT,
exclusive OR, and to the rotate and shift instructions. These instructions are all performed
in the ALU and usually affect all the flags.
3.8.1 BOOLEAN FUNCTION
Each function is performed bit by bit between the source and destination operands. CF
and OF are reset.
Example 3.6
Determine the contents of register AL and the state of the flags after the following
instructions are executed.
MOV AL, 6DH
MOV BH, 40H
AND AL, BH
Solution
First write the register contents in binary:
01101101 (AL)
01000000 (BH)
01000000 =40H (AL)
The flags are affected as follows:
CF = 0 ;CF is reset by the AND instruction
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PF = 0 ;40H has an odd number of logic 1’s
AF = x ;AF is undefined
ZF = 0 ;the result is not zero
SF = 0 ;bit is reset
OF = 0 ;OF is reset by the AND instruction
Table 3.9 logical instructions
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The applications of AND
• The destination operand can be forced low by choosing those bits as 0 in the source
operand.
• To consider the source operand a mask for testing selected bits of the destination
operand.
In the above example all bits are masked except bit 6. If this bit is 0, the result is zero, if
it is 1, the result is non zero.
AND AL, BH
JZ START
Using the AND instruction results in a “destructive” bit test because the contents of the
destination operand is altered by the instruction.
Figure 3.2 shift and rotate instructions
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TEST: this instruction performs the same function as AND instruction, but doesn’t alter
the source or destination operand. This is a particular handy instruction to use when
several bits must be tested.
OR instruction can be used to force selected bits high. Example OR AL, 80H will force
bit 7 of AL high without changing any of the other bits in this register.
Exclusive-OR can be used to complement selected bits. Example XOR AL, 80H will
complement bit 7 of register AL without changing any of the other bits.
Table 3.10 shifts and rotate instructions
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3.9 SHIFT AND ROTATE INSTRUCTIONS
There are several shift and rotate instructions. The rotated quantity can be an 8-bit or a
16-bit CPU register or memory location. The main difference between a shift and a rotate
is that the shifted bits “fall off” the end of the register, where as the rotated bits “wrap
around.” Within the shift group of instructions there are both arithmetic (SAL and SAR)
and logical (SHL and SHR) shift instructions.
The arithmetic shifts operate so that the sign bit (bit 7 or bit 15) doesn’t change when the
shift occurs. The SAL instruction in effect multiplies the data by 2 (maintaining the
correct sign), and SAR divides the data by 2. The overflow flag (OF) will be set if the
shifted quantity exceeds the limits for an 8- or 16-bit register (+127 to -128 for bytes and
+32767 to -32768 for words). The shift and rotate instructions can be repeated up to 255
times by loading register CL with the desired count.
Example 3.7
MOV CL, 5
RCL DX, CL
Will rotate the contents of register DX left 5 times through the carry
3.10 ARITHMETIC INSTRUCTIONS
The 8086/88 can add and subtract 8- and 16- bit numbers in any of the general CPU
registers, and using certain dedicated registers, perform multiplication and division of
signed or unsigned numbers.
3.10.1 ADDITION AND SUBTRACTION INSTRUCTION
There are two forms of addition and subtraction instructions. One includes the carry and
the other doesn’t. Note that the destination and source operands can be register and
register, register and memory, memory and register, immediate data and register, or
immediate data and memory.
For example, suppose we wish to add the 32 bit number in register BX:AX to the 32-bit
number DX:CX.
BX AX
+DX CX
DX CX
Although there are no 32-bit addition instructions, the problem is easily solved by the
ADC (add with carry) instruction.
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For Example ADD CX, AX ;CX CX + AX
ADC DX, BX ;DX DX + BX + CF
The first instruction does not include the carry, as there is no carry in at this point. If the
addition of AX and CX sets CF, the second addition will add this to the sum of the DX
and BX.
The SUB (subtract) and SBB (subtract with borrow) instructions work similarly, with CF
representing the borrow condition.
Table 3.11 addition and subtraction instructions
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When adding or subtracting one from a memory pointer or counter variable, the INC
(increment) and DEC (decrement) instructions should be used.
The NEG (negate) instruction forms the 2’s complement of the destination operand,
effectively reversing its sign. This is done by subtracting the destination from 0.
Example 3.8
Determine the value of AL and the value of the flags following the instruction sequence
MOV AL, 5
NEG AL
Solution
AL = 00000000 - 00000101 = 11111011 = FBH = -5.
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The flags are affected as follows:
CF = 1 ;NEG sets CF except when the operand is 0
PF = 0 ;FBH has an odd number of logic 1’s
AF = 1 ;there is a borrow out of bit 4
ZF = 0 ; the result is not 0
SF = 1 ;bit 7 is set
OF = 0 ;there is no overflow condition
The CMP (compare) instruction is useful for determining the relative size of two
operands. Normally it is followed by a conditional jump instruction such as “jump if
equal” or “jump if greater than or equal.”
3.10.2 MULTIPLICATION AND DIVISION
Multiplication and division can be performed on signed or unsigned numbers. The source
operand can be a memory location or a CPU register, but the destination operand must be
register AX (and register DX for 32-bit results). The register usage is shown in figure 3.3
for both byte and word operations. Note that the immediate operands are not allowed.
Example 3.9
Write a program to input two 8-bit unsigned numbers from input ports A0H and B0H and
output the product to 16-bit output port 7080H.
Solution
IN AL,0A0H
MOV BL, AL
IN AL, 0B0H
MUL BL
MOV DX, 7080H
OUT DX, AX
Division can be performed on the word in AX or the double word in DX:AX. The divisor
can be an 8-bit or a 16-bit memory location or CPU register. Note that the remainder is
returned in register AH or DX when the result does not come out even.
Example 3.10
Write a program to divide the unsigned word input at indirect I/O port 8000H by 500D.
Determine the result if the input data is 56,723.
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Solution
MOV DX, 8000H
MOV BX, 01F4H
IN AX, DX
DIV BX
The result is
AX = INT (56,723/500) = 113=71H and
DX = MOD (56,723/500) = 223 = 00DFH
A special problem can occur when the divisor is so small as to cause the quotient to
overflow the register dedicated to the result. For example, dividing 65,000 by 2 leaves a
result too large to fit in register AL alone. When this occurs a special divide by zero
software interrupt is automatically generated by the 8086. This causes control to be
transferred to the address stored in locations 00000-00003H.
The integer multiplication (IMUL) and division (IDIV) instructions are similar to the
unsigned forms except that the most significant bit represents the sign of the number. For
integer byte division the quotient is limited to the range +127 to -128 and to the range
+32767 to -32768 for word division.
The register usage is shown
Figure 3.3 register usage for multiplication and division instructions
The multiplication and division instructions can be performed on 8-bit or 16-bit register
or memory source operands. Specific registers are dedicated to these functions as shown.
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Table 3.12 multiplication and division instructions
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3.11 TRANSFER OF CONTROL INSTRUCTION
All programs execute in a sequential manner (fetch instruction whose address is in IP,
increment IP, and execute the instruction). However, there are times when it is necessary
to transfer program control to an address that is not the next instruction in sequence.
Examples are:
• Group of instructions that must be executed repeatedly
• Groups of instructions that are shared throughout a program (subroutine)
• Conditional transfers based on the state of the flags, and
• Software interrupts.
3.11.1 UNCONDITIONAL JUMP INSTRUCTION
There are five forms of the jump instruction. Three of them are unconditional, (control is
transferred to the target address without regard for the state of flags)
When a program control is transferred to a new address relative to the value in IP, it is
called near or relative jump (direct form). When the target address is within -128 to +127
bytes of IP, it is called short jump. Using short jump one byte of object code can be
saved. Because one less byte is required, the short form is best. In fact, when assembling
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your program, the assembler will automatically generate a short jump if it can determine
that the target address is located within -128 to +127 bytes.
The following group of instructions shows assembly language program demonstrating the
near jump instruction
ADDR HEX CODES LABELS OP-CODE OPERANDS
0000 B3 04 MOV BL, 04H
0002 E5 06 REPEAT: IN AX, 06H
0004 F6 F3 DIV BL
0006 E7 9A OUT 9AH, AX
0008 E9 F7 FF JMP REPEAT
000B
And the following program is rewritten using the JMP SHORT instruction; one byte of
code is saved.
ADDR HEX CODES LABELS OP-CODE OPERANDS
0000 B3 04 MOV BL, 04H
0002 E5 06 REPEAT: IN AX, 06H
0004 F6 F3 DIV BL
0006 E7 9A OUT 9AH, AX
0008 E9 F8 JMP SHORT REPEAT
000A
The memory indirect and register indirect forms of the jump instruction specify the actual
16-bit target address. These two forms are not thus relative.
Example JMP SHORT REPEAT instruction can be replaced with two instructions.
MOV BX, 00002
JMP BX
Note that using indirect jump, any address within the code segment can be specified.
However, an extra instruction is required to set the target address. The main advantage of
using relative jump is that the resulting program is relocatable anywhere within the code
segment.
When control is transferred to a target address in a new code segment, it is called a far
jump. Again direct and indirect forms are possible but neither form is relative. The direct
form requires the assembler operator FAR PTR to identify the label as being in a new
code segment. The indirect forms must specify a double word for the new CS and IP
values.
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Table 3.13 jump instruction
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3.11.2 CONDITIONAL JUMP
The conditional jump instructions perform a short jump based on the condition of the
status flags.
Tables below show and list all the testable conditions. Usually, a conditional jump
instruction is placed after an arithmetic or logical instruction, transferring control
depending on the result of that instruction.
Table 3.14 conditional jump instructions
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Example 3.11
Explain the operation of the following program.
MOV BL, 47H
IN AL, 36H
CMP AL, BL
JE MATCH
JA BIG
JMP SMALL
Note that MATCH, BIG, and SMALL must be located within -128 to +127bytes of the
corresponding conditional jump instruction
Solution
The program inputs a data byte from input port 36H and then compares it with 47H. If a
match occurs, control is transferred to the program beginning at address MATCH. If the
input byte is >47, control is transferred to the program beginning at address BIG. If none
of these conditions are met, control is passed to the program beginning at address
SMALL.
In summary, the conditional jump instructions are among the most important in the
processor’s instruction set, because they allow the processor to make decisions based on
program condition.
3.12 Loop instructions
Loop instructions are used to set up a group of instructions to execute several times. They
combine the decrement counter and transfer of control instruction
Decrement register which holds the loop count by 1 at the end of each loop
JNZ (jump to the start if count register is not zero)
Example 3.12
Using the loop instruction, write a program segment to output 256 bytes from data table
beginning at address TABLE to output port A0H. Assume DF=0
Solution
LEA SI, TABLE
MOV CX, 0100H
AGAIN: LODSB
OUT 0A0H, AL
LOOP AGAIN
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Table 3.15 loop instructions
This example shows the string and loop instructions actually perform two operations
each. LODSB (load string byte) is equivalent to
MOV AL, [SI]
INC SI
And LOOP AGAIN replaces the equivalent instructions
DEC CX
JNZ AGAIN
The LOOPE or LOOPZ (loop if equal or zero) and LOOPNE or LOOPNZ (loop if not
equal or not zero) instructions test CX and ZF. For example, LOOPE “loops while equal”
this means that if CX≠0 and ZF=1, the loop will be repeated. These two forms are useful
when comparing two strings or looking for a match between a CPU register and a byte or
word in a data table.
Note all forms the loop instruction repeat until CX=0, this means that the loop will be
repeated 65,536 times if CX=0 initially.
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3.13 Push and pop instructions
The PUSH and POP instructions use the stack area of the memory. Stack Segment (SS) is
a 64K-B memory segment whose base address determined by SS register. Two CPU
registers SP, and BP normally points into this area. The stack is a special area in memory
used by the processor for temporary data storage. SS segment is LIFO type of memory.
Data is pushed onto the stack by the PUSH source instruction. And the POP destination
instruction causes the data currently on top of the stack to be popped into the destination
operand. Note the stack actually grows downward with each successive PUSH
instructions.
Table 3.16 push and pop instructions
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Example 3.13
PUSH CX
PUSH BX
Registers should be popped off the stack in the reverse order in which they were pushed
on. Before using the stack it is important that register SP be initialized to a high memory
location allowing room for the stack to grow.
Finally, PUSHF and POPF instructions allow the processor flags to be stored on the
stack. This can be useful
ul with interrupts and subroutines as the entire state of the machine
(all CPU registers and flags) can be saved and then restored later.
3.14 Call and return instructions
The CALL and RET instructions allow the programmer to use a group of instructions as a
subroutine or procedure that can be executed several times from within the main
program. The CALL instruction is similar to an unconditional jump except that the value
of IP is pushed onto the stack, Control then transfer. The subroutine must end with a RET
instruction, which causes the top of the stack to be popped into IP, neatly returning
control to the instruction in the main program with which it left off.
The far CALL differs from the near CALL in that the value of CS (in addition to IP) is
saved onn the stack. For this reason a far RET instruction is used to pop CS and IP from
the stack when the far procedure has ended.
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Table 3.17 call and return instructions
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3.15 Software interrupts
An interrupt is a request of the processor to suspend its current program and transfer
control to a new program called the interrupt service routine (ISR). The interrupt request
can be initiated in hardware or software. For the 8086, applying a logic 1 to the INTR or
NMI input line will initiate the interrupt request.
Software interrupts are initiated by giving the instruction INT type. The processor
responds by pushing the flags, CS, and IP on to the stack. It then loads new value for CS
and IP from an interrupt jump table located in absolute memory from 00000 – 003FFH.
These 1KB allow 256 different software interrupt request
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Figure 3.4 Stack area after executing an INT type instruction.
SP’ is the new value of register SP
Figure 3.5 interrupt jump table
If an INT 23H is executed, the processor will multiply 23H by 4 (rotate left twice),
resulting in the jump table address 0008CH. CS and IP will then be loaded with the
double word stored in 0008CH through 0008FH (CS in the higher order word, IP in the
th
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lower order word). When ISR has finished, the IRET instruction should be executed to
pop the flag register from stack (in addition to CS and IP).
400H Type 255
3FCH Type 254
14H Type 5
10H Type 4 Over flow
CH Type 3 Break point
Type 2 NMI non maskable
8H interrupt
4H Type 1 Trap
0H Type 0 Division error
CS high byte
CS low byte
IP high byte
IP low byte
Figure 3.6 interrupt jump table
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Table 3.18 software interrupt instructions
3.16 Processor control instruction
Processor control instructions are used to control the operation of the processor and set or
clear the status indicators.
The STD (set direction flag) and CLD (clear direction flag) instructions are used to set or
clear this flag.
STI (set interrupt enable flag) and CLI (clear interrupt enable flag) enable or disable
maskable interrupts on the INTR input line. Clearing this bit blocks all interrupts on
INTR effectively masking this input.
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There is no instruction for setting or resetting TF (trap flag), but the following sequence
of instructions can be used to set TF.
PUSHF
MOV BP, SP
OR BYTE PTR[BP+1], 01H
POPF
The HALT instruction will stop the processor and cause it to enter an idle loop.
However, once halted it can be restarted only via a hardware interrupt or system reset.
Table 3.19 processor control instructions
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