Lecture 9
8254 Programmable Interval Timer (PIT)
The 8254 consists of three independent 16-bit programmable
counters (timers).
Each counter is capable of counting in binary or binary-coded
decimal (BCD).
Maximum allowable input frequency to any counter is 10 MHz
Timer appears in the PC decoded at ports 40H–43H to do the
following:
1. Timer 0: Generate a basic timer interrupt that occurs at
approximately 18.2 Hz, that interrupts the microprocessor at
interrupt vector 8 for a clock tick. Often used to time
programs and events in DOS
2. Timer 1: is programmed for 15 µs, used on the PC to
request a DMA action used to refresh the dynamic RAM.
3. Timer 2: is programmed to generate a tone on the PC
speaker.
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Lecture 9
Block Diagram of 8254 Timer
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Lecture 9
Each timer contains:
CLK: which provides input frequency to the timer
Gate: input pin which controls the timer in some modes
OUT: an output connection to obtain the output of the timer
A0, A1: The address inputs select one of four internal registers
within the 8254.
A1, A0 Selection
00 Counter 0
01 Counter 1
10 Counter 2
11 Control Register
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Lecture 9
Programming the 8254
Each counter is programmed by writing a control word,
followed by the initial count.
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Lecture 9 Modes of Operation
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Lecture 9
Mode 0
Allows 8254 to be used as an events counter.
Output becomes logic 0 when the control word is written and
remains until N plus the number of programmed counts.
Note that gate (G) input must be logic 1 to allow the counter to
count.
If G becomes logic 0 in the middle of the count, the counter will
stop until G again becomes logic 1.
Mode 1
Causes function as a retriggerable, monostable multivibrator
G input triggers the counter so it develops a pulse at the OUT
connection that becomes logic 0 for the duration of the count.
If G input occurs within the output pulse, the counter is reloaded and
the OUT connection continues for the total length of the count.
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Lecture 9
Mode 2
Allows the counter to generate a series of continuous pulses one
clock pulse wide.
For a count of 10, output is logic 1 for nine clock periods and
low for one clock period.
The cycle is repeated until the counter is programmed with a
new count or until the G pin is placed at logic 0.
G input must be logic 1 for this mode to generate a continuous
series of pulses
Mode 3
Generates a continuous square wave at the OUT connection,
provided the G pin is logic 1.
If the count is even, output is high for one half of the count and
low for one half of the count.
If the count is odd, output is high for one clocking period longer
than it is low.
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Lecture 9
Mode 4
Allows a single pulse at the output.
If count is programmed as 10, output is high for 10 clocking
periods and low for one period.
Operates as a software triggered one-shot.
As with modes 2 and 3, this mode also uses the G input to enable
the counter.
Mode 5
A hardware triggered one-shot that functions as mode 4. except it
is started by a trigger pulse on the G pin instead of by software
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Lecture 9
Q. Design an interface circuit that required to interface the 8254
to an 8 MHz 80386 so that it generates a 100 KHz square
wave at OUT0 and a 200 KHz continuous pulse at OUT1. The
8254 connected to I/O ports 0700H, 0702H, 0704H, and
0706H of an 80386.
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Lecture 9
Calculation: To generate square wave of 100KHx, then the load = 8Mhz/ 100KHz = 80
If the load is higher than 255. the data is 16 bit so value of RW1 = 1 and RW0 = 1 in Control
Register.
To generate continuous pulses of 200KHx, then the load = 8Mhz/ 200KHz = 40
MOV DX, 706H ; address control word
MOV AL, 00110110B ; program counter 0 for mode 3
MOV DX, AL
MOV AL, 01110100B ; program counter 1 for mode 2
MOV DX, AL
MOV DX, 700H ; address counter 0
MOV AL, 80 ; load count of 80 to counter 0 (low order byte)
OUT DX, AL
MOV AL, 0 ; load counter 0 with high order byte
OUT DX, AL
MOV DX, 702H ; address counter 1
MOV AL, 40 ; load count of 40 (low order byte)
OUT DX, AL
MOV AL, 0 ; load counter 1 with high order byte
OUT DX, AL
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Reading a Counter
Each counter has an internal latch read with the read counter
port operation. the latches will normally follow the count
If counter contents are needed, the latch can remember the count
by programming the counter latch control word.
Counter contents are held in a latch until read
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Read – back control word
When necessary for contents of more than one counter to be
read at the same time, the read-back control word is used.
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With the read-back control word, the CNT bit is logic 0 to
cause the counters selected by CNT0, CNT1, and CNT2 to be
latched.
If the status register is to be latched, then ST is placed at logic
0.
The status register, which shows:
the state of the output pin
whether the counter is at its null state (0)
how the counter is programmed
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