Introduction – Verilog HDL

Sridhar P
VLSI Design Process
• Design Complexity Increasing Rapidly
• IC-SSI-MSI-LSI-VLSI. Chips with more than million transistors
• Need for better design flows/ process/ representation – CAD tools/ design methodology – Standardized
design flow
• Conflicting requirements – feature set, area, power, speed of operation…
• Moore’s Law the number of transistors in an integrated circuit (IC) doubles about every two years.
[18months]

8085. 6500 transistors, 3-6 Mhz Pentium 4, 42 million Transistors, 1.3 – 3.8Ghz
VLSI Design Process – Design Flow
Physical Layout [Floor Planning, Place &
Design Specification
Route]

Behavioural Description
Timing Verification, Post layout
RTL Description

Functional Verification & Testing Layout Verification

Synthesis & Timing Verification Implementation

VLSI Design Process – CAD design Tools
• Based on Hardware Descriptor Languages
• HDLs provide the necessary formats for representing the different
design steps
• CAD Tool transforms HDL Input to HDL output with requisite
information
• Behavioral to RTL
• RTL to Gate
• Gate to Transistor
• Transistor to Layout
VLSI Design Process - HDLs
• VERILOG HDL
• VHDL [ VHSIC HDL – Very High Scale Integrated Circuit HDL]

• Advantages of HDL
• Designs are described at abstract level – without a choice of a specific
fabrication technology.
• Functional verification at HDL level is easier, thereby reducing the product life
cycle
• A textual representation of the design with comments helps in having a better
documented design
History of HDL
• Gateway design Automation in 1984
• VHDL was developed by US department of defense to Document ASIC
behaviorß
• Verilog based Synthesis developed by Synopsys 1987
• Initial version of VHDL, designed to IEEE standard IEEE 1076-
1987
• Cadence Purchased Verilog in 1989
• Verilog was inducted as the IEEE 1364 standard in 1995
Design Representation – Three Points of View
Behavioral Structural
Behavioral Physical Domain Domain
always @ (posedge clk) begin
if (! rstn)
out <= 0; Programs Gates
else Specifications Adders
out <= out + 1; Trust Tables Registers
end

Structural Transistors
layouts
Cells

Physical
Domain
Behavioral representation
module counter ( input clk, // Declare input port for clock to allow counter to count up
input rstn, // Declare input port for reset to allow the counter to be reset to 0
when required
output reg[3:0] out); // Declare 4-bit output port to get the counter values

// This always block will be triggered at the rising edge of clk (0->1)
// Once inside this block, it checks if the reset is 0, if yes then change out to zero
// If reset is 1, then design should be allowed to count up, so increment counter
always @ (posedge clk) begin
if (! rstn)
out <= 0;
else
out <= out + 1;
end
endmodule
Structural Representation
module ripple_carry_counter(q, clk, reset); module T_FF(q, clk, reset);
output q;
output [3:0] q;
input clk, reset;
input clk, reset; wire d;
//4 instances of the module T_FF are created. D_FF dff0(q, d, clk, reset);
T_FF tff0(q[0],clk, reset); not n1(d, q);
endmodule
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
Structural Representation
module T_FF(q, clk, reset); module D_FF(q, d, clk, reset);
output q; output q;
input clk, reset; input d, clk, reset;
wire d;
reg q;
D_FF dff0(q, d, clk, reset);
not n1(d, q); always @(posedge reset or negedge clk)
endmodule if (reset)
q <= 1'b0;
else
q <= d;
endmodule
Levels of Abstraction
• Each Module internals can be defined as
• Behavioral – Highest level of Abstraction, similar to C programming

• Data flow level – Module is designed specifying the data flow

• Gate Level – Module is designed as interconnection of logic gates

• Switch Level – Lowest Level of abstraction, module is defined by switches,
storage nodes and interconnections
Design Methodologies – Top Down

Top Level
Block

Sub Block Sub Block Sub Block

1 2 3

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell
Design Methodologies – Bottom Up

Top Level
Block

Macro Macro Macro

Cell 1 Cell 2 Cell 3

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell
Modules
module <Module Name> (<module terminal list>) ;
module
Inputs
module internals ; Module 1

endmodule
module
endmodule
Module 2
Design Block
endmodule
module

Module 3

endmodule
Outputs
Stimulus Block Top Level Block

Stimulus Block

Stimulus Block

Design Block

Outputs

Outputs
Simulate
• Free Software Available
• ICARUS Verilog
• GTKWave

sudo apt install iverilog gtkwave

Link to Install Icarus Verilog and GTKWave in ubuntu Linux

https://www.youtube.com/watch?v=nY150XXEj6M

Download Ubuntu24.04 LTS

Verilog Language – Basic Concepts
• White Space : \b, \t, \n are white spaces and generally ignored by Verilog except
in strings
• Comments :
• // One line comment
• /* Multi lines Comment */
• Operators:
• Unary : a = ~b ;
• Binary : c = a&&b ;
• Ternary: a= b?c:d ;
• Numbers: <size>’<base format><number>
• 8’b10101101
• 16’hDFAC
• 16’d255
• Numbers without a base format is decimal by default. Without size is treated as
32 bit or as per the m/c
Verilog Language – Basic Concepts
• Numbers :
• X is used to indicate unknown
• Z is used to indicate high impedance
• - sign before the size indicate negative number
• _ (underscore) can be used to improve readability. Cannot be used in the beginning
• ? Is an alternative for Z.
• String:
• “ hello Verilog”
• Keywords : Special Identifiers to define language constructs. Lower case
• Identifiers : names given to objects to be referenced in the design
Input Clk; “ Input is Keyword and Clk is identifier”
\”a+b+c” is an identifier (from \ to whitespace)
Verilog Language – Basic Concepts
Value Levels Strength Levels
Value Level Condition Strength Type Degree
0 Logic 0 Level
1 Logic 1 Supply Driving Strongest
X Unknown Strong Driving
Z High Pull Driving
Impedance Large Storage
Weak Driving
Medium Storage
Small Storage
Highz High Weakest
Impedance
 Data Variables
• Vectors : net or reg data types can be
declared as vectors
• Net : • wire [7:0] abus
• Connections between hardware
elements • reg [15:0] addr;
• Continuously driven • Variable Vector Part Select
• Defined by Keyword wire
• [<starting_bit>+:width] - part-select increments from
• Default value is z starting bit
• wire a;
• [<starting_bit>-:width] - part-select decrements from
• Registers: starting bit
• Represent data storage reg [31:0] data1 ; // little endian notation
• Retain the value assigned last
reg [0:31] data2 ; //big endian notation
• Defined by Keyword reg
• Default value is x byte = data1[31-:8] ; //w=8 and data1[31:24]
• reg reset; byte = data1[24+:8]; //w=8 and data1[31:24]
• Can be integer, real or time byte = data2[31-:8]; //w=8 and data2[24:31]
• Integer count
byte = data2[24+:8]; //w=8 and data2[24:31]
Data Variables
• Arrays:
• reg [15:0] addr [7:0] ; // 8 nos of 16 bit addr of type register
• integer matrix [7:0] [7:0] ; / 2 dimensional array of integers 8x8
• reg [7:0] addr [15:0] [7:0] [31:0] ; /* 3 dimensional array with each entry
being 8 bit wide of type register */
• integer Count [7:0] ; // array of 8 count variables
• A vector is a single element that is n-bits wide. On the other hand, arrays are
multiple elements that are 1-bit or n-bits wide.
Data Variables
• Parameter
• Used to define constants in a module
• parameter port_id = 0 ; //defines a constant port id as 0
• parameter cache_line_width = 64 ; //defines cache_line_width as 64 bits

module Block ; module Top ;

parameter port_id
=0; Block #(1) B1; // in B1 Instance port_id = 1
Block #(2) B2 ; // in B2 instance port_id = 2
module internals
endmodule module internals
endmodule
Data Variable
• String
• There is no specific String data type in Verilog
• Strings can be stored in Reg.
• The width should be large enough to store the string

reg [8*24:1] string_name ; // variable that is 24 byte wide

System Tasks
$display is the main system task for displaying values of variables or strings or expressions
$display(p1, p2, p3,....., pn);
//Display value of 41-bit virtual address 1fe0000001c at time 200.
reg [0:40] virtual_addr;
$display ("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c

$monitor task provides a mechanism to monitor a signal when its value changes.
$monitor(p1,p2,p3,....,pn);
$monitoron; $monitoroff;

• $stop task is provided to stop during a simulation. Suspends

• $finish task terminates the simulation.
• $dumpfile specifies the file for storing the waveform
• $dumpvars starts dumping signals to the specified file
Compiler Tasks
`define directive is used to define text macros in Verilog
'define WORD_REG reg [31:0] ;

`include directive allows you to include entire contents of a Verilog

source file in another Verilog file during compilation.
'include “header.v” ;
Modules
Module Name
Port List, Port Declarations
Parameters (Optional)

Declarations of Dataflow
wires, regs and statements
other variables assign

Lower Level modules always, Initial Blocks

Instantiation Behavioral Statements

Tasks and Functions

endmodule
Ports Verilog Keyword Type of Port
Input Input Port
Output Output Port
Inout Bidirectional Port
IN [3:0]
Out
Mux4to1 net
SEL[1:0]
net inout

Port
reg or net
input Connection output
net
net Rules reg or net
 `include "mux4to1.v"
module tb_mux4to1;
wire tout;
Mux4to1 reg [3:0] tin ;
reg [1:0] tsel ;
mux4to1 m0 ( .out(tout),
module mux4to1 ( output reg out, input [3:0] in, .in(tin),
input [1:0] sel); .sel(tsel));
initial begin
always @ (sel or in)
$dumpfile("waveform_mux.vcd” );
begin $dumpvars(0, tb_mux4to1);
case (sel) tin <= 4'b0000;
2'b00: out = in[0]; tsel <= 2'b00;
2'b01: out = in[1]; #20 tsel <= 2'b01;
2'b10: out = in[2]; #20 tin <= 4'b0101;
#40 tsel <= 2'b10;
2'b11: out = in[3];
#60 tsel <= 2'b11;
default: out = 1'bx; #80 tin <= 4'b1010;
endcase #100 tsel <= 2'b01;
end #120 tsel <= 2'b10;
endmodule #140 tsel <= 2'b11;
#20 $finish;
end
Port Connections
• Connections ports by ordered list
• mux4to1 m0 (tout, tin, tsel);

• Connections ports by name

• mux4to1 m0 ( .out(tout), .in(tin), .sel(tsel));

Hierarchy names tb_mux4to1

root level

tb_mux4to1.m0.out
Tb_mux4to1.tout mux4to1 tout, tin[3:0], tsel[1:0]
mo

out, in[3:0], sel[1:0]

Primitive Verilog Gates
wire OUT, IN1, IN2; wire OUT, IN1, IN2;
and a1(OUT, IN1, IN2); buf b1(OUT1, IN);
nand na1(OUT, IN1, IN2); not n1(OUT1, IN);
or or1(OUT, IN1, IN2); bufif1 b1 (out, in, ctrl);
nor nor1(OUT, IN1, IN2); bufif0 b0 (out, in, ctrl);
xor x1(OUT, IN1, IN2); notif1 n1 (out, in, ctrl);
xnor nx1(OUT, IN1, IN2); notif0 n0 (out, in, ctrl);
Verilog Operators
Type Symbols Operation Number of Operands
Arithmetic *, /, +, -, %, ** Mul, div, add, sub, mod, exp, Two
Logical !, &&, || Negation, and, or One, Two, Two
Relational >, <, >=, <= GT, LT, GTE, LTE Two
Equality ==, !=, ===, !=== Equality, Inequality, Case Eq, Two
Case Ineq
Bitwise ~, &, |, ^, ^~ or ~^ Bitwise neg, and, or, xor, xnor One, two
Reduction &, ~&, |, ~|, ^, ~^ And, nand, or, nor, xor, xnor one
Shift >>, <<, >>>, <<< Right, left, arithmetic right, Two
arithmetic left
Concatenation {} Any number
Replication {{}} Any Number
Conditional ?: Three
Operators Precedence
Operator
Unary
Mul, div, mod
Add, Sub
Shift
Relational
Equality
Reduction
Logical
Conditional
Continuous Assignment
• A continuous assignment is the most basic statement in dataflow
modeling, used to drive a value onto a net
• Regular Continuous assignment
• wire [3:0] sum, a, b;
• wire c_out, c_in ;
• assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
• Implicit Continuous assignment
• wire out = in1 & in2 ;
Procedures
• Structure Procedures
• Initial
• Statements inside an initial statement constitute an initial block.
• An initial block starts at time 0, executes exactly once during a simulation, and then does not
execute again.
• If there are multiple initial blocks, each block starts to execute concurrently at time 0.
• Each block finishes execution independently of other blocks.
• Multiple statements must be grouped, typically using the keywords begin and end
• Always
• Statements inside an always statement constitute an always block.
• The always statement starts at time 0 and executes the statements in the always block
continuously in a looping fashion.
• This statement is used to model a block of activity that is repeated continuously in a digital
circuit.
Structure Procedures : Initial and Always
initial begin always @(posedge reset or
$dumpfile("waveform.vcd"); negedge clk)
$dumpvars(0, tb_counter); if (reset)
clk <= 0;
rstn <= 0; q <= 1'b0;
#20 rstn <= 1; else
#80 rstn <= 0; q <= d;
#50 rstn <= 1;
#20 $finish;
end
Procedural Assignments
• Procedural assignments update values of reg, integer, real, or time
variables.
Blocking Assignments: Executed in the order Non Blocking Assignments: for concurrent data
they are specified in a sequential block transfers
reg a, b, c; reg a, b, c;
reg [7:0] reg_a, reg_b; reg [7:0] reg_a, reg_b;
int Count; int Count;
begin begin
a =0 ; b = 1; z = 1; a =0 ; b = 1; z = 1;
Count = 0 ; Count = 0 ;
#15 reg_a = 8’b0; reg_a <= #15 8’b0;
#10 reg_b = reg_a ; reg_b <= #10 reg_a ;
Count = Count + 1 ; Count = Count + 1 ;
end end

Non blocking assignments eliminate race conditions

Gate delay 1

• Rise delay
0, x, z
t_rise
1, x, z

• Fall delay
0
t_fall
1, x

• Turn off delay z

0, x

• Min delay: minimum value and # (min_rise:typ_rise:max_rise,

min_fall:typ_fall:max_fall,
• Typ delay : Typical Value min_toff:typ_toff:max_toff) a1 (out, in1, in2) ;
• Max delay : Maximum Value
Delay based timing control
• Regular delay : # Delay_Value reg_a = 8’b10101010 ;
• Intra assignment delay : a = # Delay_Value b+ c ;
• Zero delay control: ensures statement is executed last : #0 x = 1 ;
• Regular Event Control: @(Clock) q = d ; @(posedge clock) q = d ;
• Event Or Control (Sensitivity List): @(reset or clock or d) begin .. end
• Sensitivity list with @* : always @(*) ….
Conditional Statements – Multiway branching
• If (<expression>) • case (<expression>)
• True statement1; • alternative1: statement 1;
• else if (<expression>) • alternative2: statement 2;
• True statement2; • alternative3: statement 3;
• …………………………………….;
• ……. • …………………………………….;
• ……. • …………………………………….;
• else default statement; • default: default_statement;

Casex, Casez
Loops
• While Loop • For Loop • Repeat
integer count; integer count; integer count;
initial initial initial
begin begin
begin
count = 0; Repeat(128)
for(i = 0; i < 32; i = i + 1)
while (count < 128) begin
Statements ;
Statements ; Statements ;
end end
count = count + 1;
end end

Forever Loop
Tasks and Functions
• Task • Function
• Declared with keyword Task • Declared with keyword function and
and Endtask endfunction
• Used when there is delay, • Used when there is no delay, event
event control or timing control or timing constructs in procedure
constructs in procedure • Procedure returns a single value
• Has either none or more • At least one input
than 1 output args • No output or inout
• No input • No nonblocking assignments
Task & Functions
• Task • Function
task bitwise_oper; function calc_parity;
output [15:0] ab_and, ab_or, ab_xor;
input [31:0] address;
input [15:0] a, b;
begin
begin
ab_and = a & b; calc_parity = ^address;
ab_or = a | b; end
ab_xor = a ^ b; endfunction
end
endtask parity = calc_parity(addr);

bitwise_oper(AB_AND, AB_OR, AB_XOR,

A, B);
Tasks & Functions

A function can enable another function but not A task can enable other tasks and functions.
another task.
Functions always execute in 0 simulation time. Tasks may execute in non-zero simulation time.

Functions must not contain any delay, event, or timing Tasks may contain delay, event, or timing control
control statements. statements.
Functions must have at least one input argument. Tasks may have zero or more arguments of type input,
They can have more than one input. output, or inout.
Functions always return a single value. They cannot Tasks do not return with a value, but can pass multiple
have output or inout arguments. values through output and inout arguments
Sequential Logic Design

Combinatorial Next State Current State

Logic State
Inputs Register
Output Mealy Model

Clock Output
Inputs
Reset
Combinatorial
Moore Model Logic Next State
State Current State
Clock Register

Reset
Timing Checks

Clock

Data
Setup hold
 Use of Blocking/ Non-Blocking assignments in
Sequential logic Non-blocking
always @(posedge clk) begin
module test_reg (clk, in1, out1) ; reg1 <= in1;
reg2 <= reg1;
input clk, in1;
out1 <= reg2 ;
output out1; end
blocking
reg reg1, reg2, out1;
always @(posedge clk) begin
reg1 = in1; in1
in1 d q d q d q
d q out1 out1
reg2 = reg1; clk
out1 = reg2 ; clk clk clk clk clk

end
endmodule
Encoder
module encoder (in0, in1, in2, in3, sel);
input in0, in1, in2, in3;
output [1:0] sel ;
reg [1:0] sel ;
always @(in0, in1, in2, in3) begin
sel = 2b’00; Use Case statement or in System Verilog unique if
if (in0) sel = 2’b00;
elseif(in1) sel = 2’b01;
elseif(in2) sel = 2’b10;
elseif(in3) sel = 2’b11;
end
endmodule;
Priority Encoder
Latch
module encoder (in1, out, sel); module mux4to1 ( output reg out, input [3:0] in,
input [1:0] sel);
input in, sel; always @ (sel or in)
output out1 ; begin
case (sel)
reg out1; 2'b00: out = in[0];
always @(in1, sel) begin 2'b01: out = in[1];
2'b10: out = in[2];
if sel = 1’b1;
// 2'b11: out = in[3];
out = in1; // default: out = 1'bx;
endcase
end
end
endmodule endmodule
Re-Usable Coding Practices
• Register all the outputs of crucial design blocks. This will make the timing
interface easy during system level integration
• Avoid snake paths, as it will make both debugging tedious and synthesis
inefficient.
• Partition the design considering the clock domains and the functional
goals.
• Follow lexical and naming conventions that are self-descriptive and
facilitate future product maintenance.
• Avoid instantiation of technology specific gates
• Use parameters instead of hard-coded values in the design
• Avoid clocks and resets that are generated internal to the design
• Avoid glue logic during top level inter-module instantiations
Some Resources
• Verilog HDL: A Guide to Digital Design and Synthesis, Second
Edition By Samir Palnitkar

• Verilog: Frequently Asked Questions ,Language, Applications and

Extensions by Shivakumar Chonnad Needamangalam Balachander
Icarus Verilog
• iverilog -o Counter.vvp tb_Counter.v
• vvp Counter.vvp
• gtkwave waveform.vcd