Introduction to Verilog HDL
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Tutorial Outline
• Introduction
• VLSI Design flow
• Circuit Modeling
• Gate-level Modeling
• Data-level Modeling
• Behavioral Modeling
• Testing & Simulation
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VLSI DESIGN FLOW
A design flow is a sequence of operations that transform the
IC designers’ intention (usually represented in RTL format)
into layout GDSII (Graphic Design System) data.
A well-tuned design flow can help designers go through the
chip-creation process relatively smooth and with a decent
chance of error-free implementation.
A skilful IC implementation engineer can use the design flow
creatively to shorten the design cycle, resulting in a higher
likelihood that the product will catch the market window.
VLSI Design of approach of IC
Front-end design (Logical design):
1. Design entry – Enter the design in to an ASIC design system
using a hardware description language (HDL) or schematic entry.
2. Logic synthesis – Generation of net list (logic cells and their
connections) from HDL code.
Logic synthesis consists of following steps: (i) Technology
independent Logic optimization (ii) Translation: Converting
Behavioral description to structural domain (iii) Technology
mapping or Library binding .
3. System partitioning - Divide a large system into ASIC-sized
pieces.
4. Pre-layout simulation - Check to see if the design functions
correctly. Gate level functionality and timing details can be verified.
Back-end design (Physical design):
5. Floor planning - Arrange the blocks of the netlist on
the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and
blocks
8. Circuit Extraction - Determine the resistance and
capacitance of the interconnect
9. Post-layout simulation - Check to see the design still
works with the added loads of the interconnect
Partioning
Introduction
• What is Verilog HDL?
Verilog HDL is a Hardware Description
Language that can be used to model a
digital system at many levels of
abstraction:
– Algorithmic-level
– Gate-level
– Switch-level
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Where can we use Verilog HDL?
• Verilog is designed for circuit simulation and
verification, for timing analysis, for test
analysis (testability analysis and fault grading)
and for logic synthesis.
• For example, before you get to the structural
level of your design, you want to make sure
the logical paths of your design is faultless
and meets the required specifications.
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Basics of Verilog HDL
• Module & its syntax
• Basics of Verilog
• Modeling styles
– Gate Level
– Data flow
– Behavioral
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Basic Syntax of a Module
Module module_name (port_list);
Declarations:
input, output, wire, parameter…..
System Modeling:
describe the system in gate-level, data-flow, or
behavioral style…
endmodule
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Basic Module Construction
// Compute the logical AND and OR of
inputs A and B.
module AND_OR(andOut, orOut, A, B);
output andOut, orOut;
input A, B;
and (andOut, A, B);
or (orOut, A, B);
endmodule
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Structural models of combinational logic
• Verilog primitives for design
encapsulation
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List of declarations wire connected
primitives
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Format of Verilog module
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Verilog structural models
• Module ports
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Language rules
• Verilog is a case sensitive language
– Eg: AND_OR & and_or names are different.
– Verilog has 7 types of lexical tokens- operators,
keywords, identifiers, white spaces, comments,
numbers, and strings.
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• Keywords
module -- signifies the beginning of a module
definition.
endmodule -- signifies the end of a module
definition.
begin -- signifies the beginning of a block of
statements.
end -- signifies the end of a block of statements.
if -- signifies a conditional activity to be checked
while -- signifies a conditional activity to be carried
out.
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• Identifiers
– It is good practice for us to use identifiers,
closely related to the significance of
variable, signal, block, etc., concerned.
This eases understanding and debugging
of any program.
– There are some restrictions in assigning identifier
names. All characters of the alphabet can be used
as the first character. Subsequent characters can
be of alphanumeric type, or the underscore (_), or
the dollar ($) sign.
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• for example name, Name, name1, name_$, . . . -- all
these are allowed as identifiers
• name aa -- not allowed as an identifier because of
the blank ( “name” and “aa” are interpreted as two
different identifiers)
• $name -- not allowed as an identifier because of the
presence of “$” as the first character. 1_name -- not
allowed as an identifier, since the numeral “1” is the
first character
• @name -- not allowed as an identifier because of the
presence of the character “@”. A+b m not allowed as
an identifier because of the presence of the character
“+”.
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• White Space Characters
– Blanks (\b), tabs (\t), newlines (\n), and
form feed form the white space characters
in Verilog
• to improve readability.
• Functionally, they separate legal tokens
• They are introduced between keywords,
keyword and an identifier, between two
identifiers, between identifiers and operator
symbols, and so on.
• White space characters have significance only
when they appear inside strings.
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• Comments
– Comments can be inserted in the code for
readability and documentation.
– There are two ways to write comments
• a = b && c; // This is a one-line comment
• /* This is a multiple line
comment */
• /* This is /* an illegal */ comment */
• /* This is //a legal comment */
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• X or Z values
– for modeling real circuits.
– An unknown value is denoted by an x.
– A high impedance value is denoted by z.
Example:
– 12'h13x // This is a 12-bit hex number; 4
least significant bits unknown
– 6'hx // This is a 6-bit hex number
– 32'bz // This is a 32-bit high impedance
number
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• Value Set or Logic Values
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• Strengths
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• Datatypes
– Nets
– Variable
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• Operators
– Operators are of three types: unary, binary,
and ternary.
– Unary operators precede the operand.
Binary operators appear between two
operands.
– Ternary operators have two separate
operators that separate three operands.
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• Examples of operators
– a = ~ b; // ~ is a unary operator. b is the
operand
– a = b && c; // && is a binary operator. b and
c are operands
– a = b ? c : d; // ?: is a ternary operator. b, c
and d are operands
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• Number Specification
Sized :
–4'b1111 // This is a 4-bit binary number
– 12'habc // This is a 12-bit hexadecimal
number
–16'd255 // This is a 16-bit decimal number.
Unsized:
eg: 23456 // This is a 32-bit 'hc3 //
This is a 32-bit 'o21 //
This is a 32-bit decimal number by default
* hexadecimal number octal number 31
Vectors in Verilog
• Vectors in Verilog denoted by square
brackets, enclosing a contiguous range
of bits.
• Eg:
– Sum[3:0]
– Input[3:0]
– Output[7:0]
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Modeling styles of Verilog
• Data flow
• Behavioral
• Gate Level
• Structural
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Data-flow Modeling
• The basic mechanism used to model a
design in the dataflow style is the
continuous assignment.
• In a continuous assignment, a value is
assigned to a net.
• Syntax:
assign #delay LHS_net = RHS_expression;
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Example: 2 to 4 Decoder
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Example
module Decoder 2_4(Z,A,B,EN);
Input A,B,EN;
output [3:0] Z;
wire Ab, Bb;
assign #1 Ab=~A;
assign #1 Bb=~B;
assign #2 Z[0]=~(Ab & Bb & EN);
assign #2 Z[1]=~(Ab & B & EN);
assign #2 Z[2]=~(A & Bb & EN);
assign #2 Z[3]=~(A & B & EN);
endmodule
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Behavioral Modeling
• The behavior of a design is described
using procedural constructs. These are:
– Initial statement: This statement executes
only once.
– Always statement: this statement always
executes in a loop forever…..
• Only register data type can be assigned
a value in either of these statements.
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Always Statement
• Syntax: always
#timing_control procedural_statement
• Procedural statement is one of :
– Blocking Procedural_assignment
always
@ (A or B or Cin)
begin
T1=A & B;
T2=B & Cin;
T3=A & Cin;
Cout=T1 | T2 | T3;
end
T1 assignment is occurs first, then T2, then T3….
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Procedural statements
Conditional_statement
always
@(posedge clk or posedge reset)
if ( Sum <60)
begin
Grade = C;
Total_C=Total_C +1;
end
else if (Sum<75)
Grade = B;
else
Grade = A;
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Procedural statements
Case_statement
always
@(Time ==7)
case(Day)
Tue: Pocket-Money = 6;
Mon,
Wed: Pocket_Money = 2;
Fri,
Sat,
Sun: Pocket_Money = 7;
default: Pocket_Money= 0;
endcase
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Gate-Level Modeling
Systems structure can be described using Build-in
gates or pre-built modules.
Basic syntax is :
gate-type #delay instance1_name(outputs.., inputs.. ),
:
:
instance6_name(outputs.., inputs.. );
pre-built module module_instance1(output…,inputs..);
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The Built-in Primitive Gates
• Multiple-input gates:
– and, nand, or, nor, xor, xnor
xor xor1(out, inA, inB, inC);
• Multiple-output gates:
– buf, not
not inverter1(fanout1, fanout2, in);
• Tristate gates:
– bufif0, bufif1, notif0, notif1
bufif0 tbuffer1(out, in, control);
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Gate Delays
• Syntax: #(Tplh, Tphl)
• Examples:
nor #10 Tplh =Tphl=10 time units
nor #(3,5) Tplh=3, Tphl=5
nor #(2:3:4, 5) Tplh=(min2,typ3,max4)
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Example: A 4 to1 Multiplexer
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Simple Example
module Mux4_1 (Z, D,S);
output Z;
input [3:0] D;
input [1:0] S;
wire S0b, S1b, T0, T1, T2, T3;
not #5 inv0(S0b, S[0]),
inv1(S1b, S[1]);
and #10 and0(T0, D[0], S1b, S0b),
and1(T1, D[1], S1b, S[0]),
and2(T2, D[2], S[1], S0b),
and3(T3, D[3], S[0], S[1]);
or #10 or1(Z, T0,T1,T2,T3);
endmodule
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Structural style:
Top down design and nested modules
Eg: Full adder
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16-bit Ripple carry adder using 4-bit
ripple carry adders
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Design hierarchy of 16 bit RCA
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Structural connectivity - Wires
• Wires in Verilog establish connectivity
between design objects.
• They connect primitives to other primitives
and/or modules.
• Or they connect modules to other modules
and/or primitives
• The variable Wire is a member of family of
nets
– Establish connectivity in a design
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Formal and actual names for port
association by name in module
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Eg: 2-bit Comparator:
- compares two 2-bit numbers and
asserts the relation > or < or =
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Schematic of 2-bit Comparator
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Verilog code (Gate level modeling style)
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4-bit Comparator
using two 2-bit comparators
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Verilog code (Structural style)
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Logic System, Design verification
and Test methodology
• Two methods of verification are used
– Logic simulation
• applies stimulus patterns to a circuit and
monitors its simulated behavior to determine
whether it is correct or not.
– Formal verification
• uses elaborated mathematical proofs to verify
circuit’s functionality without need to apply
stimulus pattern
*Currently, Logic simulation is still widely used
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Four value logic
• 0, 1, X, Z
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Test Methodology
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• A Simulator performs three essential
tasks.
– 1) Checks the source code
– 2) reports any violation of source code
– 3) simulates the behavior of the circuit
under the application of input signals
defined in the test bench
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Example of Test bench
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Signal generators for Testbenches
• The keyword, initial declares a single
pass behavior
– that begins executing when the simulator is
activated at tsim = 0.
– The statements associated with behavior
are listed within the begin …… end block
keywords
• called as Procedural statements
• = is procedural assignment operator
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Simulator output waveforms
Eg: Half adder
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Event driven simulation
• A change in the value of a signal
(variable) during simulation is referred
to as an “event”.
• Event driven simulation
– computational activity of simulators is
driven by propagation of events in a circuit
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Test bench Template
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Sized numbers
• The values assigned to the stimulus
waveforms in the testbench can be
sized numbers
• Eg: 8’ha : 8-bit hexa decimal no. a
• Four formats are available
– Binary (b)
– Decimal (d)
– Octal (o)
– Hexadecimal (h)
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Propagation delay
• The delay between the time that an input
changes and the time that the output
responds to change
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Inertial delay
• The amount of time that the input pulse must
be constant in order for the gate to make a
transition is called the inertial delay of the
gate.
• Verilog uses the Propagation Delay (PD) of a
gate as the minimum width of an input pulse
that could effect the output
– It also considered as inertial delay.
– Inertial delay has the effect of suppressing input
values whose duration is shorter than PD of the
gate.
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Transport delay
• The time-of-flight of a signal travelling a
wire of a circuit is modeled as a
Transport delay.
– Narrow pulses are not suppressed
– All transitions at the driving end of a wire
appear at the receiving end after a finite
time delay.
– Wire delays
• Eg: wire #2 A_long_wire
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Truth table models of combinational &
sequential logic with verilog
• A mechanism for building User Defined
Primitives (UDP)
uses Truth Tables to describe sequential
behavior and/or more complex
combinational logic.
UDPs are widely used in ASIC cell
libraries
As they simulate faster and requires less
storage than modules.
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Example: AOI gate (5-input)
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Eg: UDP for 2-input Multiplexer
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Short hand notation: 2x1 MUX
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UDP for Latch
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UDP for D-Flip flop
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UDP for J-K flip flop
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Further References:
– A Verilog HDL Primer by J. Bhasker
– Verilog HDL: A Guide to Digital Design and
Synthesis by Samir Palnitkar
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