S

r. Learning Objectives LAB No.

Overview of Verilog 0
1 Installation 1

Logic gates
0
2 AND, OR, NOT, XOR 2

Multiplexer
Adder
0
Subtractor
3 3

Encoder 0
4 Decode 4

Flip Flops
0
5 D,JK, and T 5

4 Bit Register
0
6 Create a 4-Bit synchronous counter 6

4 Bit ALU
0
7 Operations (ADD,SUB,AND,OR,XOR) 7

0
8 Shift and comparison operations in ALU 8
 Memory Design
0
9 RAM, ROM 9

Instruction set
1 1
Operations : load, store, add, subtract, jump
0 0
Implement fetch and decode logic

1 1
1 1
Datapath Design

1 ALU, register, memory, interface 1

2 2
Control Unit Design

1 Manage instruction execute 1

3 3

1 1
Integrate the ALU, Control unit, and memory into a single system
4 4
Project

1 1
5 5
Project

1 1
6 6
 LAB 1

OVERVIEW OF VERILOG

What is Verilog?

Verilog is a hardware description language (HDL) used to model electronic systems. It is primarily used in
the design and verification of digital circuits, such as microprocessors, memory chips, and other digital logic
circuits.

The circuits were described using schematics in the past two decades. The advent of complex and high-
speed digital and analog designs made it difficult to think and design on schematic level. This urged a
strong need for a language which can model and simulate hardware as good as schematic. This oriented
HDL (hardware descriptive language) which can describe any circuit using language constructs. There are
several HDLs including Verilog HDL, VHDL (very high-speed integrated circuit hardware description
language), SystemC and others. Verilog will be used for purpose of this book, due to its easiness and
similarity to C.
Verilog is hardware descriptive language,
i.e. a language equipped to model and simulate hardware. Although verilog HDL is a language, it isn't an
ordinary programming language. Every construct in Verilog models hardware; therefore it must be
understood using hardware concepts. The design is initially written in verilog , then it is tested using a
software environment called simulation. Once the design is tested it is translated into hardware known as
synthesis. The summary of the whole discussion is: “Every statement in verilog models hardware and like
other programming languages it has constructs including loops, logic structures etc.”
 INSTALLATION STEP 1:
Access Intel's ModelSim Download Page

● Open your browser and navigate to the Intel download link.

● Image: A screenshot of the browser window showing the Intel ModelSim download page.
https://www.intel.com/content/www/us/en/software-kit/750368/modelsim-intel-fpgas-standard -edition-
software-version-18-1.html
 STEP 2:
CONFIRM DOWNLOAD
• Confirm the download and save the file to your system.
• Image: Download progress window
 STEP 3:
Download the Installer

• Click on the License is not required button and wait for the ModelSim installer to finish
downloading.
• Image: A download confirmation or progress bar.
 STEP 4:
LICENSE AGREEMENT

• Accept the license terms to proceed with the installation.

• Image: A screenshot showing the installer being launched.
 STEP 5:
FOLLOW INSTALLATION PROMPTS

● Accept the license agreement and follow the prompts to select the installation location.
● Image: A dialog box showing license agreements or folder selection.
STEP 6:
SUMMARY
The software will install the necessary files. Wait for the process to complete.
 STEP 7:
INSTALLATION IN PROGRESS

• The installer will proceed to install the necessary files. Wait for the progress bar to complete.
• Image: Installation Progress bar

STEP 8:
 LAUNCH MODELSIM

• After installation, open ModelSim from your applications menu or desktop.

• Image: The ModelSim software interface after a successful installation.
 BASIC STRUCTURE FOR PROGRAMING

WRAPPER FOR PROGRAMING

Verilog is based on a basic wrapper which is used in every program. The wrapper consists of a
module and an end-module containing all programming logic. Module in Verilog is the smallest
programming entity. They can also be called like functions in other languages (instantiation in
Verilog). The basic structure of wrapper used in every Verilog program

As said before that every statement in Verilog models hardware, so the wrapper is just like a chip
packaging with name printed on it and logic contained. The user logic is most important part of the
design; it defines a structure which maps input to output according to specified logic. The details of user
logic will be discussed in coming sections.

PORT LIST

The second basic aspect in every design is port list. The port list connects the user logic to
external world. It includes inputs and outputs. In hardware port list is just like pins on the chip boundary,
which connects circuit inside the chip to external world. Consider a design which xor two inputs and
generates output. In example 2-2 design with two inputs and one output is discussed.

The name of the module in design example 2-2 is My_Xor. It contains one output ‘Xor_Out’ and two
inputs ‘
Xor_In1’ and ‘Xor_In2’. There may be many other internal variables inside the design. The port list
only contains those variables which require connection to the external world and internal variables aren’t
part of the port lists.

PORT DEFINITION

It is required to define that ports are input or output i.e. direction of the port. Once port
direction is defined, the next question is; what is the width of the port i.e. is it bus or a scalar (one
bit)? This section of code is essential in every design; it must be the starting point of the code. In
this section scalar IO’s are considered and focus is kept on direction only. In order to specify
direction of ports, two keywords input and output are used. Verilog is case sensitive so input and
output must be in small letters. The analogy to real world IC is through data sheets, IC’s also
define port list, and each pin in chip has direction, these port directions are specified in datasheet.
We can understand Verilog port list concept through real world
IC data sheet
 The alternative style is to provide port definition in the port list as shown in example 2-3b. This reduces the

number of lines in the code however it also makes code less readable. Design given in example 2-3a is

followed

in this chapter

NAMING CONVENTION AND VERILOG

Certain rules must be abided by while declaring variables, naming modules and using other
naming in Verilog. The naming conventions are the same as that in C or most programming
languages. Following are naming conventions:
1- The name can’t start with a number, for example 2x1Mux is an incorrect name for design. The possible
alternative is Mux2x1.
2- It must not contain any white spaces. All letters must be connected, or can be punctuated using
underscore.
3- Names can’t use Verilog specific keywords/built- in primitives. Verilog primitives and keywords can be
seen from annexure-A of the book.
4- The name can’t contain special characters, however underscore can be used.

Verilog is case sensitive language while naming it must be kept in mind. All keywords are small
therefore names with naming can be done using primitives/keywords if alternative cases are used. It is
advised to use clear and concise naming convention so that design is more readable and other
 developers can easily grasp it. Clarity in code and naming reduces programming error, makes code
more readable and testable, therefore integration of multiple76 modules becomes easy and reliable.
The naming must also coincide with design specification and documentation so that code and design
blocks can’t be reviewed back and forth.

Data flow modeling:

Data flow modeling is a very popular style of coding in Verilog. In larger designs, chunks are
written n data flow for two reasons.

1. Where there is no delay and immediate assignments are required. Outputs aren’t forced by any input
conditions. For example, think of Flip Flop, there are two outputs q and qbar, the latter is always inverted.
There is no condition involved; we always assign q bar equals inverse of q.
2. Where we have very simple combinational circuit elements and we don’t want to model them at a behavior
level. Usually this is required in resolving synthesis constraints, and we model few behavioral constructs in
dataflow to bypass constraint problems.

Data flow modeling mostly uses mathematical operators to model a certain Boolean expression. Digital
design mostly starts with some logic given in truth tables, which are minimized by K maps or Boolean
reduction. This results into Boolean expressions which are ultimately to be translated into gates. Gate level
modeling thinks designs in term of gates while dataflow thinks designs in Boolean expressions. So what
difference does it make in thinking both ways? Below is the answer of the posed question:

Operators and basic rules in data flow:

Gate level circuits are modeled using predefined primitive gates, which are already discussed. In a similar
way the armory of data flow is operators, below are operators used in data flow. The operators are
categorized as unary , arithmetic and logical operators, which are used for different purposes. We will use
these operators to construct and device the functionality of each logic function in a data flow model. Table
2-8 presents Unary operators, such operators take only single operand.

Table defines arithmetic operators, each operator takes two operands. The operators are given in terms of
their precedence. Each operation is performed using a single statement containing RVAL(right hand side
value) and LVAL(left hand side value). When an expression is evaluated the right hand side expression is
computed using operators. The result of an operation is assigned to the left hand side of the statement.
The operators mentioned in table 2-8 and table 2-9a are common operators which are mostly found in C++.
Verilog allows some additional operators, which are listed in table 2-9b. The shift operator >> allows
shifting of operand, the shift amount can be specified using a scalar number, for example A=A<<2 means
that shift A twice and store the result in A.
Verilog allows concatenation operators, which can combine two or more variables together. To understand
{,} concatenation operators consider a full adder example. In case of full adder two 4 bit numbers FA_In1
and FA_In2 are added together the result is a 5 bit number which is stored in 4 bit FA_Sum and 1-bit
FA_Cout. Both FA_Sum and FA_COut are combined together using a concatenation operator .
 LAB 2
LOGIC GATES

AND GATE:

Theory:
The OR gate is a digital logic gate that implements logical disjunction. The OR gate outputs "true" if
any of its inputs is "true"; otherwise it outputs "false". The input and output states are normally
represented by different voltage levels.

Symbolic Diagram:

Truth Table:
A B Y

0 0 0

0 1 1

1 0 1

1 1 1
 ModelSim Work:
module
or_gate (
input A, //
Input A
input B, //
Input B output
Y // Output Y
);
// Gate-level modeling of OR gate
or (Y, A, B);
endmodule

Explanation:

● Inputs: A and B are the two input signals to the AND gate.
● Output: Y is the result of the logical AND operation between A and B.
● assign: This keyword is used to drive the output with a combination of inputs.

When A and B are both 1, the output Y will be 1; otherwise, it will be 0.

Activity-2 Outcomes:
To understand Boolean logic of AND gate

Theory:

1. The OR gate is a basic digital logic gate that implements logical conjunction (∧) from mathematical
logic – OR gate behaves according to the truth table. A HIGH output (1) results only if all the inputs
to the OR gate are HIGH (1). If not all of the inputs to the AND gate are HIGH, a LOW output
results.
 Symbolic Diagram:

Truth Table:
A B Y

0 0 0

0 1 0

1 0 0

1 1 0

ModelSim Work:

module and_gate

( input A, // Input

A input B, //

Input B output Y

// Output Y

);

// Gate-level modeling of

OR gate and (Y, A, B);

endmodule

Activity-3 Outcomes:
To understand Boolean logic of NOT gate

Theory:
A NOT gate, often called an inverter, is a nice digital logic gate to start with because it has only a
single input with simple behavior. A NOT gate performs logical negation on its input. In other
words, if the input is true, then the output will be false. Similarly, a false input results in a true
output.

Symbolic Diagram:

Truth Table:
A Y

0 1

0 0

ModelSim Work:
module not_gate

( input A, // Input

A output Y //

Output Y

);

// Gate-level modeling of NOT

gate not (Y, A);

Endmodule
Activity-4 Outcomes: To understand
Boolean logic of XOR gate Symbolic
Diagram:

Truth Table:

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

MultiSim Work:

module xor_gate (
input A, // Input A
input B, // Input B
output Y // Output
Y

);
 // Gate-level modeling of XOR
gate xor (Y, A, B);

endmodule

Exercise:-
Write down NOT Gate Program

a) Write down OR Gate Program

b) Write down AND Program

c) Write down XOR Program

 LAB # 3
Multiplexer Adder Subtractor

Statement:

Designing of

Multiplexer using logic

gate

Activity Outcomes:
To understand Boolean logic of 4:1 multiplexer

Theory:

Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs but
only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit that is
selected. The general multiplexer circuit has 2n input signals, n control/select
signals and 1 output signal.

Output: Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

Symbolic Diagram:
Truth Table
4*1 multiplexer:

A 4-to-1 multiplexer (4:1 MUX) is a combinational circuit that selects one of four input
signals (in0, in1, in2, or in3) and forwards it to a single output line based on the values of two selection
lines (sel[1] and sel[0]). Each combination of selection inputs allows only one input to pass through by
enabling the corresponding AND gate, while the others remain inactive. The outputs of these AND gates
are combined using an OR gate, which determines the final output. This selective data routing makes the
4:1 MUX a fundamental building block in digital circuits for managing and directing data flow efficiently.

CODE:

module mux_4to1 (

input wire [1:0] sel,

input wire in0, in1,

in2, in3, output wire

out

);

wire not_sel0, not_sel1; wire

and0, and1, and2, and3; not

(not_sel0, sel[0]); not

(not_sel1, sel[1]); and (and0,

in0, not_sel1, not_sel0); and

(and1, in1, not_sel1, sel[0]);

and (and2, in2, sel[1],

not_sel0); and (and3, in3,

sel[1], sel[0]); or (out, and0,

and1, and2, and3);

endmodule

2*1 multiplexer:
A 2-to-1 multiplexer (2*1 MUX) is a digital switch that selects one of two input signals to
pass to the output based on the value of a control signal. It has two data inputs (often labeled as \(A\) and
\(B\)), one control input (or select line, \(S\)), and a single output. When the select line \(S\) is 0, the
multiplexer outputs the value at input \(A\); when \(S\) is 1, it outputs the value at input \(B\). This device
is commonly used in digital circuits to route data from multiple sources into a single data line, enhancing
the circuit's flexibility and efficiency.

CODE:

module

mux_2to1 (

input wire sel,

input wire

in0, in1,

output wire

out

);

wire not_sel, and0,

and1; not (not_sel,

sel); and (and0, in0,

not_sel); and (and1,

in1, sel); or (out,

and0, and1);

endmodule
Activity-1 Outcomes: Theory:
Adder: Digital computer perform a variety of information processing tasks, among the basics function
encountered are the various arithmetic operations, the most basic arithmetic operation no doubt is the
addition b of two binary digits, this simple addition consists of four possible elementary operations
which namely as
0+0=0

0+1=1

1+0=1

1+1=10

Half Adder: A combinational circuit that performs the addition of two bits is called the half adder; one
that performs the addition of three bits(two significant bits and a previous carry) is called a full adder.
I used the IC 74LS08 and IC 74LS86 to check the operation of half adder and I also used the two
switches to prove that the ic is working.I connected the the switch a with 1a pin of ic and switch b with
the 1b of ic and I provided the 5v vcc to the switches .Then I connected the 1y pin of IC with LED. As
the IC is working with the operation so when the both inputs are 1 than the sum is 0 and the carry is 1
where as when both inputs are 0 then the sum and carry are 0.The above logic operation of the half gate
can be summarized with the help of truth table

Symbolic Diagram:

Truth Table:
A B S C

0 0 0 0
 0 1 1 0

1 0 1 0

1 1 0 1
MultiSim Work:

module
Half_adder(sum,carry,in1,in2);
input in1,in2; output sum,carry;
xor (sum,in1,in2); and
(carry,in1,in2); endmodule
''''''''''''''''''''''''''''''''''''
module full_adder
(sum,carry,in1,in2,cin); input
in1,in2,cin; output sum,carry; wire
w_ha1,w_ha1c,w_ha2C;

Half_adder
HA1(w_ha1,w_ha1c,in1,in2);
Half_adder
HA2(sum,w_ha2c,w_ha1,cin); or
o1(carry,w_ha1c,w_ha2c);

endmodule

Designing half subtractor and full subtractor Activity-1

Outcomes:
To understand Boolean logic of half subtractor

Theory:
Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a difference bit D and a
borrow out bit Br. This operation is called half subtraction and the circuit to realize it is called a half
subtractor. The Boolean functions describing the half Subtractor are:

Symbolic Diagram:

Truth Table:
A B S C

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Multisim:
module half_subtractor (
input wire A, // Minuend (A-B)

input wire B, // Subtrahend (A

B) output wire Diff, //Difference
output
output wire Bout // Borrow output
);

// Difference= A XOR
B assign Diff = A ^ B;

// Borrow = NOT A AND B

assign Bout = (~A) & B;

endmodule

Testbench:

module HalfSubtractor(difference,borrow,a,b);

output
difference,borrow; input
a,b;

wire A;

xor
o1(difference,a,
b); not o2(A,a);
and
o3(borrow,A,b);

endmodule
—---------------------------------------------------------module TB_Subtractor; wire t_difference,t_borrow; reg
t_a,t_b;
HalfSubtractor
HalfSubtractor(.b(t_b),.a(t_a),.difference(t_difference),.borrow(t_borrow)); initial
begin

t_a=1'
b0;
t_b=1
'b0;
#5
t_a=1'
b0;
t_b=1
'b1;
#5
t_a=1'
b1;
t_b=1
'b0;
#5
t_a=1'
b1;
t_b=1
'b1;
end
endm
odule
 LAB # 5

Truth Table verification of Flip flops

D type FlipFlop.
1)T type FlipFlop.
4) JK Flip Flop.

Activity Outcomes:
To realize and implement

Theory:

Logic circuits for digital systems are either combinational or sequential. The output of combinational
circuits depends only on the current inputs. In contrast, a sequential circuit depends not only on the
current value of the input but also upon the internal state of the circuit. Basic building blocks (memory
elements) of a sequential circuit are the flip-flops (FFs). The FFs change their output state depending upon
inputs at a certain interval of time synchronized with some clock pulse applied to it. Usually any flip-flop
has normal inputs, present state Q(t) as circuit inputs and two outputs; next state Q(t+1) and its
complementary value; Q`. We shall discuss the most widely used latches that are listed below.

D Flip Flop:
T Flip Flop
JK Flip Flop
 LAB # 6

4 Bit Register

Create a 4-Bit synchronous counter

The goal of this lab task is to design and simulate a 4-bit Arithmetic Logic Unit (ALU) that performs five
basic operations: addition, subtraction, AND, OR, and XOR, using Verilog.

An ALU (Arithmetic Logic Unit) is a key component of any processor or digital system, responsible
for performing arithmetic and logical operations. A 4-bit ALU can take two 4-bit inputs and perform
operations such as addition, subtraction, bitwise AND, OR, and XOR, based on a control signal
(opcode).

Operations:

• Addition (A + B)
 • Subtraction (A - B)

• AND (A & B)

• OR (A | B)

• XOR (A ^ B)

• Inputs: o A and B: Two 4-bit

inputs for the ALU.
o opcode: A 3-bit control signal used to select the operation. The ALU will perform
different operations based on the value of the opcode.
• Operations (opcode values): o 000 – Addition (A +
B) o 001 – Subtraction (A - B) o 010 – AND (A & B)
o 011 – OR (A | B) o 100 – XOR (A ^ B)
• Outputs: o result: A 4-bit output representing the result of
the operation.

LAB # 7

Shift and comparison operations in ALU

Activity Outcomes:
Shift and Comparison Operations
in ALU Objective:
Understand and implement shift and comparison operations in a 4-bit Arithmetic Logic Unit (ALU).
These operations include shifting bits left or right and comparing values for equality or magnitude.

Shift Operations:

1. Left Shift (<<):

o Shifts the bits of the operand to the left.
o Each left shift operation effectively multiplies the number by 2. o Example: 4'b0011 << 1 results in
4'b0110.

2. Right Shift (>>):

o Shifts the bits of the operand to the right.
o Each right shift operation effectively divides the number by 2, discarding any remainder.
o Example: 4'b1100 >> 1 results in 4'b0110.

Comparison Operations:
1. Equality Check (==):
• Compares two values to determine if they are equal.
• Outputs 1 (true) if the values are equal, otherwise 0 (false)

• Example: 4'b1010 == 4'b1010 results in 1.

2. Greater-than Check (>):
• two values to determine if the first value is greater than the second.
• Outputs 1 (true) if the first value is greater, otherwise 0 (false). o Example:
4'b1010 > 4'b0110 results in 1

LAB # 8

Memory Design: RAM and ROM

Activity Outcomes:

Memory Design: RAM and ROM

Objective:

Understand and implement memory designs using Verilog, focusing on RAM (Random Access
Memory) and ROM (Read-Only Memory). The RAM allows data to be read and written
dynamically, while ROM allows only reading of data stored at compile-time.

RAM Design:

1. RAM (Random Access Memory):

o RAM is a type of volatile memory where data can be read from and written to at specific
 addresses. o In this implementation, we use 16 memory locations,
each storing 8 bits of data.

ROM Design:

1. ROM (Read-Only Memory):

o ROM is a non-volatile memory that stores predefined data. It can only be read and not written
to
during runtime.
o In this example, the ROM is initialized with data at compile-time and supports only read
operations.
2. Part 1: RAM Implementation:
Implement a 16x8 RAM module in Verilog, which can store 16 memory locations,
each holding
8-bit data.
o Write the Verilog code to read and write data at a specific memory address. o Create a
testbench to:

1. Write data to two different addresses.

2. Read data back from those addresses and verify correctness.
3. Part 2: ROM Implementation:
o Implement a 16x8 ROM module in Verilog. o Initialize the ROM with some predefined values (at
least 4 different values). o Write the Verilog code to read data from ROM at any given address.
o Create a testbench to:
1. Read data from three different addresses.
2. Ensure that the correct data is returned for each address.
4. Part 3: Comparison:
o Write a brief description of the differences between RAM and ROM based on the Verilog
implementations.
o Explain when to use RAM vs ROM in a real-world system.
 LAB # 9

Instruction Set

Activity Outcomes:
Instruction Set

Objective:

Understand and implement basic instructions in a processor-like structure using Verilog. The
instructions will perform simple operations such as loading, storing, arithmetic operations (add,
subtract), and jumping to different parts of the instruction sequence.

Operations:

1. Load:
o Loads a value from a memory location into a register.
o Example: load R1, 100 (Load the value from memory address 100 into register R1).
2. Store:
o Stores a value from a register into a memory location.
o Example: store R2, 200 (Store the value from register R2 into memory address 200). 3.
Add:
o Adds two register values and stores the result in a destination register.

o Example: add R1, R2, R3 (R1 = R2 + R3).

4. Subtract:
o Subtracts one register value from another and stores the result in a destination
register. o
Example: sub R1, R2, R3 (R1 = R2 - R3).
5. Jump:
o Jumps to a specific address in the instruction memory. o Example: jump 50 (Jump
to instruction at address 50).
 Implementation in Verilog:

You can implement this using a basic processor model with an instruction memory, registers, and a
control unit to execute the operations.

Explanation:

1. Program Counter (pc): Points to the current instruction in memory.

2. Instruction Memory: Stores the instructions to be executed.
3. Registers (R1, R2, R3): Hold values for arithmetic and memory operations. 4.
Memory: Stores both data and instructions for load and store operations.
 LAB # 10

Implement Fetch and Decode Logic

Activity Outcomes:

Implement Fetch and Decode

Logic Objective:

Understand and implement the fetch and decode stages of a simple processor in Verilog. These stages
are crucial in the instruction cycle for fetching instructions from memory and decoding them to execute
specific operations.

Instruction Cycle:

1. Fetch:
o The process of retrieving an instruction from memory. The address of the instruction is typically held in the
Program Counter (PC).
o After fetching, the PC is incremented to point to the next instruction.
2. Decode:
o The process of interpreting the fetched instruction.
o The instruction is divided into opcode (which determines the operation) and operands (which
provide data or memory addresses for the operation).

Explanation:

1. Program Counter (PC):

o Points to the current instruction in memory.
o Increments after each instruction fetch.
2. Instruction Memory:
o A simple memory array holding instructions.
o Each instruction is 8 bits, where the upper 4 bits represent the opcode and the lower 4 bits
represent the operand.
3. Fetch Stage: o The instruction at the address in the PC is fetched
from memory.
4. Decode Stage:
o The instruction is split into the opcode and operand.
o The opcode is used to determine what operation to perform, and the operand provides data or
addresses.
 LAB # 11

Statement:

Datapath Design

Activity Outcomes:
Datapath Design

Objective:

Understand and design the datapath of a simple processor, which includes components like the
Arithmetic Logic Unit (ALU), registers, memory, and the interface between these elements.

Key Components of the Datapath:

1. Arithmetic Logic Unit (ALU):

o Performs arithmetic and logic operations (e.g., add, subtract, AND, OR, etc.).
o Receives operands from the registers and provides results to the registers or memory. 2.
Registers:
o Small, fast storage units that hold operands for the ALU and store the results temporarily. o A set of
registers, such as the accumulator and general-purpose registers, is crucial for efficient processing.
3. Memory:
o Stores data and instructions that are fetched during execution.
o The memory interface allows for reading/writing data to/from the ALU and registers. 4.
Interface:
o The control unit manages data flow between registers, ALU, and memory.
o It sends control signals that dictate operations like fetch, decode, execute, and write-back.

Explanation:
1. ALU: Handles arithmetic and logical operations based on the opcode.
2. Register File: A small set of registers for quick data storage and retrieval.
3. Memory: Provides a larger storage space for data and instructions.

53

4. Datapath Interface: Combines the components, where data flows between registers, ALU, and memory.
The control signals orchestrate the operations.
 LAB # 12

Statement:

Control Unit Design

Activity Outcomes:
Control Unit Design

Objective: Understand and design the control unit (CU) of a processor, which manages instruction
execution by generating the necessary control signals for the datapath components.

Key Responsibilities of the Control Unit:

1. Instruction Fetch: o Fetches the instruction from memory

using the Program Counter (PC).
2. Instruction Decode:
o Decodes the fetched instruction to determine the operation to be performed.
3. Control Signal Generation:
o Generates control signals to direct the operation of the ALU, registers, and memory. 4.
Instruction Execution:
o Executes the operation based on the decoded instruction and generated control signals.

Components of the Control

Unit:

1. Instruction Register (IR):

o Holds the current instruction being executed.
2. Program Counter (PC):
o Holds the address of the next instruction to be fetched.
3. Control Signals:
o Signals to control the operation of the ALU, registers, memory, and other components.
4. Finite State Machine (FSM):
o Manages the sequence of operations (fetch, decode, execute) and transitions between different
states.

Explanation:

1. State Machine:
o FETCH: Fetches the next instruction from memory. o DECODE: Decodes the instruction to
determine the operation.
o EXECUTE: Executes the operation based on the opcode and control signals.
2. Control Signals:
o opcode: Determines the operation to perform.
o reg_write: Enables writing to registers. o mem_write: Enables writing to memory.
o mem_read: Enables reading from memory.
3. FSM Logic:
o Transitions between states based on the current state and instruction.
 LAB # 13

Statement:

Integration of ALU, Control Unit, and Memory

Activity Outcomes:
Integration of ALU, Control Unit, and Memory

Objective:

Combine the ALU, Control Unit, and Memory into a cohesive system to perform complex instructions.
This system should handle instruction fetching, decoding, execution, and memory operations.

System Overview:

1. ALU: Performs arithmetic and logic operations.

2. Control Unit: Directs the operation of the ALU, registers, and memory based on
the current instruction.
3. Memory: Stores instructions and data, providing read/write access.

System Architecture:

Program Counter (PC):

Holds the address of the next instruction to be fetched.
Instruction Register (IR):
Stores the currently fetched instruction.
Control Unit (CU):
Manages the instruction execution process.
 ALU: o Performs the operations based on control
signals.
1. Registers:
o Temporary storage for operands and results.
2. Memory: o Stores instructions and data.

Explanation:

1. Program Counter (PC):

o Keeps track of the next instruction address.
o Increments or updates based on the current execution stage.
2. Memory: o Stores and retrieves instructions and data.
3. Control Unit (CU):
o Fetches instructions, decodes them, and generates control signals for ALU, memory, and
registers.
4. Register File:
o Manages data storage and retrieval for the ALU operations.
5. ALU: o Performs arithmetic and logic operations as directed by the control signals.