MODULE 3: SEQUENTIAL CIRCUITS

Table of Content
 Difference between combinational and sequential circuit, Latch, flip flop: SR, JK, D and
T flip flops- Truth tables
 Excitation table, Conversion of flip flops setup and hold time race around condition
Master Slave flip flop
 Shift register SIPO, PISO, PIPO
 Bi-Directional, 4-bit universal shift register
 Counter: Asynchronous/ripple & synchronous counters-up/down
 Ring counter, Johnson counter
 Sequence detector.

DIFFERENCES BETWEEN COMBINATIONAL AND SEQUENTIAL CIRCUITS ARE:

Key differences Combinational Circuits Sequential Circuits
Memory They have no memory. Their They have memory elements
outputs depend only on the (like flip-flops) that can store
current inputs. state information.

Output Dependence Combinational circuit outputs Sequential circuit outputs

depend solely on current depend on both current inputs
inputs. and the circuit's current state.

Feedback They do not have feedback They often include feedback,

paths where outputs can affect
future states.
Clock They do not require a clock They typically use clock
signal. signals to coordinate state
changes.

Design Complexity They are generally simpler to They are more complex due
design. to timing considerations and
state management.
Examples Adders, Multiplexers, Counters, Registers, Finite
Decoders State Machines.

SEQUENTIAL CIRCUIT
A sequential circuit is a type of digital circuit that uses memory to store information about its
past states. Here's a simple and precise explanation:
Features of sequential circuits:
1. Memory: They have memory elements (usually flip-flops) to store past states.
2. Inputs and outputs: The output depends on both current inputs and the stored state.
3. Feedback: Information from the output is fed back to influence future states.
4. Clock: Often uses a clock signal to coordinate state changes.
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Main components:
1. Combinational logic: Made up of logic gates (AND, OR, NOT, etc.) to process inputs.
2. Memory elements: Typically flip-flops, used to store the circuit's state.
3. Feedback path: Connects the output back to the input, allowing past states to influence
future outputs.

Latch
A latch in digital electronics is a simple memory device that can store one bit of information (0
or 1).
Characteristics of Latch:
 Storage: Holds a single bit of data.
 Two states: Set (1) and Reset (0).
 Asynchronous: Operates without a clock signal.
 Immediate response: Changes state as soon as input is applied.
 Feedback: Maintains its state until a new input is received.
 Built from: Basic logic gates.
 Use: Fundamental memory element in digital circuits.

Latches are called bistable multivibrators due to their two stable states. Their output updates
based on input changes, making them responsive but potentially unstable in certain situations.

Types of Latches

The following are the main types of latches that used in digital circuits and systems −
1. SR Latch
2. JK Latch
3. D Latch
4. T Latch

1. SR Latch
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The SR latch is a type of latch which has two input lines designated as S and R. Where, S
represents the Set input and R represents the Reset input. Thus, it is also known as Set-Reset
Latch.
The SR latch has two stable states namely Set state (S) and Reset state (R). The block diagram of
the SR latch is shown in the following figure.

In the case of SR latch, the S input sets the output Q to 1 and Q' to 0. On the other hand, the R
input sets the output Q to 0 and Q' to 1. In case, when both S and R inputs are high, the latch is
said to be in forbidden (banned) state.
The complete operation of the SR latch for different input combinations is described in the
following truth table −
Inputs Outputs Comment
S R Q Q'
0 0 Q Q' No change
0 1 0 1 Reset state
1 0 1 0 Set state
1 1 X X Forbidden state

The SR latch can be implemented by connecting two NOR gates in a cross-coupled manner as
shown in the following figure.

2. JK Latch

The JK latch is another type of latch which has two inputs namely, J and K. Here, the input J is
similar to S input and the input K is similar to R input in an SR latch.
The operation of the JK latch is similar to that of the SR latch but it does not have the forbidden
state. Instead, it has a toggle state in which the outputs Q and Q' swap their states when both
inputs J and K are 1.
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Therefore, the JK latch is mainly designed to overcome the problem of forbidden (banned) state
in the SR latch.
The block diagram of the JK latch is shown in the following figure −

The truth table given below describes the operation of the JK latch for different input
combinations −
Inputs Outputs Comment
J K Q Q'
0 0 Q Q' No change
0 1 0 1 Reset state
1 0 1 0 Set state
1 1 Q' Q Toggle state

From this truth table, it is clear that the problem of forbidden state is addressed by implementing
the toggle state.
The logic circuit of the JK latch consists of a combination of two NOR gates and two AND gates
as shown in the following figure.

3. D Latch

The D Latch, also known as Data latch or transparent latch, is a type of bistable multivibrator
which has two input signals namely, D (Data) input and E (Enable) input.
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The output Q of the D latch is same as the input applied at the D input line as long as the E input
is high. When the E input goes low, the output of the D latch is held as it is until the new input is
applied to the D input.
The block diagram of the D latch is shown in the following figure.

The truth table given below explains the operation of the D latch −
Inputs Outputs Comment
D E Q Q'
0 0 Q Q' No change
0 1 0 1 Reset state
1 0 Q Q' No change
1 1 1 0 Set state

The logic circuit diagram of the D latch is depicted in the following figure −

4. T Latch

T latch is a type of latch that toggles its output state (Q) when a logic 1 is applied to its input
line. Hence, it is also known as toggle latch.
The T latch is implemented by connecting the J and K inputs of the JK latch together as shown in
the following block diagram.
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The truth table describing the operation of the T latch is shown below −
Input Present State Next State
T Q Q' Q Q'
0 0 1 0 1
0 1 0 1 0
1 0 1 1 0
1 1 0 0 1

The logic circuit diagram of the T latch is shown in the following figure −

FLIP-FLOP
A flip-flop is a sequential digital electronic circuit having two stable states that can be used to
store one bit of binary data. Flip-flops are the fundamental building blocks of all memory
devices.

Types of Flip-Flops
1. S-R Flip-Flop
2. J-K Flip-Flop
3. D Flip-Flop
4. T Flip-Flop
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1. S-R Flip-Flop

This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R). When in this
circuit when S is set as active, the output Q would be high and the Q' will be low. If R is set to
active then the output Q is low and the Q' is high. Once the outputs are established, the results of
the circuit are maintained until S or R get changed, or the power is turned off.

Truth Table of S-R Flip-Flop

S R Q State
0 0 0 No Change
0 1 0 Reset
1 0 1 Set
1 1 X

Characteristics Table of S-R Flip-Flop

S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

Characteristics Equation of S-R Flip-Flop

Q(t+1) =S+R′Q(t)

2. J-K Flip-Flop
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Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need of
another flip-flop. The JK flip-flop operates with only positive or negative clock transitions. The
operation of the JK flip-flop is similar to the SR flip-flop. When the input J and K are different
then the output Q takes the value of J at the next clock edge.
When J and K both are low then NO change occurs at the output. If both J and K are high, then at
the clock edge, the output will toggle from one state to the other.

Truth Table of JK Flip-Flop

J K Q State
0 0 0 No Change
0 1 0 Reset
1 0 1 Set
1 1 Toggles Toggle

Characteristics Table of JK Flip-Flop

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Characteristics Equation of JK Flip-Flop

Q(t+1)=jkQ(t)′+K′Q(t)

3. D Flip-Flop
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In a D flip-flop, the output can only be changed at positive or negative clock transitions, and
when the inputs changed at other times, the output will remain unaffected. The D flip-flops are
generally used for shift-registers and counters. The change in output state of D flip-flop depends
upon the active transition of clock. The output (Q) is same as input and changes only at active
transition of clock

Truth Table of D Flip-Flop

D Q
0 0
1 1

Characteristics Equation of D Flip-Flops

Q(t+1)=D

4. T Flip-Flop

A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained by

connecting the J and K inputs together. The flip-flop has one input terminal and clock input.
These flip-flops are said to be T flip-flops because of their ability to toggle the input state.
Toggle flip-flops are mostly used in counters.
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Truth Table of T Flip-Flop

T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

Characteristics Equation of T Flip-Flop

Q(t+1)=T′Q(t)+TQ(t)′=T⊕Q(t)

Applications of Flip-Flops
 Counters
 Shift Registers
 Storage Registers, etc.

EXCITATION TABLE: An excitation table is a tool used in digital logic design. It shows what
inputs are needed for a flip-flop to transition from its current state to a desired next state. This is
crucial for understanding how to control flip-flops in circuit design.
CONVERSION OF FLIP-FLOPS: Different types of flip-flops (like SR, JK, D, and T) can be
converted into each other using additional logic gates. This is useful when you have one type of
flip-flop available but need the functionality of another. The excitation table helps in determining
the logic needed for these conversions.
SETUP TIME: Setup time is a critical timing parameter in flip-flops. It's the minimum amount
of time the data input must be stable before the active edge of the clock for the flip-flop to
reliably capture the data. Violating setup time can lead to metastability or incorrect operation.
HOLD TIME: Hold time is the complement to setup time. It's the minimum amount of time the
data input must remain stable after the active clock edge. This ensures the flip-flop has enough
time to properly latch the data. Violating hold time can also cause incorrect operation.
RACE AROUND CONDITION: This is a problem specific to asynchronous SR flip-flops.
Because there's no clock to synchronize changes, a change in output can feed back to the input
before the flip-flop has settled, causing unwanted state changes. This "race" between feedback
and settling time can lead to unpredictable behavior.
MASTER-SLAVE FLIP-FLOP: This design solves the race around problem by using two
stages:
 The master stage captures input data when the clock is high.
 The slave stage transfers the master's data to the output when the clock goes low.
Note :
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To read more about above mentions topics, please refer link :

https://www.tutorialspoint.com/digital-electronics/digital-electronics-conversion-of-flip-
flops.htm "Digital Electronics - Conversion of Flip-Flops"

REGISTERS:

 A register is a group of flip-flops used to store multiple bits of digital data.

 Each flip-flop in a register stores one bit.
 An n-bit register can store an n-bit word (e.g., a 4-bit register can store 4 bits).

SHIFT REGISTERS

The binary data in a register can be moved within the register from one flip-flop to another. The
registers that allow such data transfers are called as shift registers. There are four mode of
operations of a shift register.

1. Serial In - Serial Out (SISO):

a. Data enters one bit at a time.
b. Data exits one bit at a time.
c. Data shifts through all flip-flops.
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2. Serial In - Parallel Out (SIPO):

a. Data enters one bit at a time.
b. All data bits are available at once at the output.
c. Useful for converting serial data to parallel.

3. Parallel In - Serial Out (PISO):

a. All data bits enter at once.
b. Data exits one bit at a time.
c. Has two modes: load (input data) and shift (output data).

4. Parallel In - Parallel Out (PIPO):

a. All data bits enter at once.
b. All data bits are available at once at the output.
c. Simplest type, used for temporary storage.
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BIDIRECTIONAL SHIFT REGISTER

If a binary number is shifted left by one position, then it is equivalent to

multiplying the original number by 2. Similarly, if a binary number is shifted
right by one position, then it is equivalent to dividing the original number by
2.
Hence if we want to use the shift register to multiply and divide the given
binary number, then we should be able to move the data in either left or
right direction.
Such a register is called bi-directional register. A four-bit bi-directional shift
register is shown in fig.
There are two serial inputs namely the serial right shift data input DR, and
the serial left shift data input DL along with a mode select input (M).
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UNIVERSAL SHIFT REGISTER

A shift register which can shift the data in only one direction is called a uni-
directional shift register. A shift registers which can shift the data in both
directions is called a bi-directional shift register. Applying the same logic, a
shift register which can shift the data in both directions as well as load it
parallelly, is known as a universal shift register. The shift register is capable
of performing the following operation −

 Parallel Loading
 Left Shifting
 Right Shifting

The mode control input is connected to logic 1 for parallel loading operation
whereas it is connected to 0 for serial shifting. With mode control pin
connected to ground, the universal shift register acts as a bi-directional
register. For serial left operation, the input is applied to the serial input which
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goes to AND gate-1 shown in figure. Whereas for the shift right operation,
the serial input is applied to D input.

Shift Register Applications:

1. Parallel to Serial Conversion: Used in transmitters after analog-to-

digital conversion.
2. Serial to Parallel Conversion: Used in receivers before digital-to-analog
conversion.
3. Sequence Generation: Creates patterns of 0s and 1s.
4. Counters: Used to create special types of counters.

Two types of counters using shift registers:

1. Ring Counter:
a. Uses a Serial In - Parallel Out (SIPO) shift register.
b. Output of the last flip-flop connects to the input of the first.
c. Produces a repeating sequence every N clock cycles for N bits.
d. Example: 3-bit ring counter sequence: 001 → 100 → 010 → 001
(repeats)

2. Johnson Ring Counter (also called Twisted Ring or Switch Tail

Ring Counter):
a. Similar to Ring Counter, but uses inverted output of last flip-flop
as input to first.
b. Produces a repeating sequence every 2N clock cycles for N bits.
c. Example: 3-bit Johnson ring counter sequence: 000 → 100 → 110
→ 111 → 011 → 001 → 000 (repeats)
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Both counters are useful for creating specific repeating patterns in digital
circuits, with applications in timing, control systems, and signal generation.

Counter
It is a sequential circuit. A digital circuit which is used for a counting pulse is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied. Counters are of two types.

 Asynchronous or Ripple Counters

 Synchronous Counters

1. Asynchronous or Ripple Counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are
being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1.
External clock is applied to the clock input of flip-flop A and Q A output is applied to the clock
input of the next flip-flop i.e. FF-B.

Block Diagram

Operation

Sr. Condition Operation

No
1 Initially let both QBQA = 00 initially
the FFs be in the
reset state
2 After 1st negative As soon as the first negative clock edge is applied, FF-A will
clock edge toggle and QA will be equal to 1.
QA is connected to clock input of FF-B. Since QA has changed
from 0 to 1, it is treated as the positive clock edge by FF-B. There
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is no change in QB because FF-B is a negative edge triggered FF.

QBQA = 01 after the first clock pulse.
3 After 2nd negative On the arrival of second negative clock edge, FF-A toggles again
clock edge and QA = 0.
The change in QA acts as a negative clock edge for FF-B. So it
will also toggle, and QB will be 1.
QBQA = 10 after the second clock pulse.
4 After 3rd negative On the arrival of 3rd negative clock edge, FF-A toggles again and
clock edge QA become 1 from 0.
Since this is a positive going change, FF-B does not respond to it
and remains inactive. So QB does not change and continues to be
equal to 1.
QBQA = 11 after the third clock pulse.
5 After 4th negative On the arrival of 4th negative clock edge, FF-A toggles again and
clock edge QA becomes 1 from 0.
This negative change in QA acts as clock pulse for FF-B. Hence it
toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock pulse.

Truth Table

2. Synchronous Counters

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.

2-bit Synchronous Up Counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The J B
and KB inputs are connected to QA.
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Block Diagram

Operation

Sr. Condition Operation

No
1 Initially let both the QBQA = 00 initially.
FFs be in the reset
state
2 After 1st negative As soon as the first negative clock edge is applied, FF-A will
clock edge toggle and QA will change from 0 to 1.
But at the instant of application of negative clock edge, QA ,
JB = KB = 0. Hence FF-B will not change its state. So QB will
remain 0.
QBQA = 01 after the first clock pulse.
3 After 2nd negative On the arrival of second negative clock edge, FF-A toggles
clock edge again and QA changes from 1 to 0.
But at this instant QA was 1. So JB = KB= 1 and FF-B will
toggle. Hence QB changes from 0 to 1.
QBQA = 10 after the second clock pulse.
4 After 3rd negative On application of the third falling clock edge, FF-A will
clock edge toggle from 0 to 1 but there is no change of state for FF-B.
QBQA = 11 after the third clock pulse.
5 After 4th negative On application of the next clock pulse, QA will change from 1
clock edge to 0 as QB will also change from 1 to 0.
QBQA = 00 after the fourth clock pulse.

Classification of Counters

Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −

 Up Counters
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 Down Counters
 Up/Down Counters

UP/DOWN Counter

Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit is
required to be designed and used between each pair of flip-flop in order to achieve the up/down
operation.

Application of Counters

 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.

SEQUENCE DETECTOR
A sequence detector is the digital circuit that detects some input signal sequences from a set of
the binary data. One can determine whether incoming bits are equal to a prestored sequence, thus
widely used in communication systems, data processing, and digital signal processing.
Meanwhile, implemented through several technologies, among them, state machines, and
programmable logic devices, sequence detectors have applications in digital electronics and
telecommunications. This technology can be applied in the area of bioinformatics, by detecting
specific nucleotide sequences in DNA or RNA, thus showing its applicability across various
fields. Sequence detector is of two types:

1. Overlapping
2. Non-Overlapping
In an overlapping sequence detector, the last bit of one sequence becomes the first bit of the next
sequence.
In a non-overlapping sequence detector, the last bit of one sequence does not become the first bit
of the next sequence.

Applications:

 Data Transmission
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 Pattern Recognition0
 Robotics