SEQUENTIAL CIRCUITS
Sequential circuit are circuits whose output depends not only on the
combination of present inputs but also on the previous output. It is
a combinational circuit that has a feedback line. It has memory
(storage) elements.
What makes sequential circuit differs from combinational circuit
1. Output depends on bith present inputs and present state
(previous input)
2. Feedback path is present
3. Memory elements are required
4. Clock signal is required
5. Difficult to design
Types of sequential circuits
1. Synchronous
2. Asynchronous Sequential Circuits:
The difference of synchronous to asynchronous sequential circuits is
that some or all the outputs do change with respect to active
transition of clock signal
What is a clock signal?
Clock signal is a periodic signal and it’s ON
time and OFF time needs not be the same.
It is represented as square wave when both
its ON time and OFF time are the same.
Types of triggering
a) Level triggering: represent two levels of clock signal (High and
Low). These can be positive level triggering and negative level
triggering.
b) Edge triggering: represents two transitions in clock signal
from Low to High or High to Low. These can be positive edge
triggering and negative edge triggering.
There are two types of memory elements based on the type of
triggering that is suitable to operate it.
a) Latches: level sensitive
b) Flip-Flop: edge sensitive
SR-Latch
SR-Latch (aka Set Reset Latch) affects
the output as long as the enable E is
maintained at ‘1’.
The circuit has two inputs S and R and
two outputs Q(t) and Q(t)’. The upper
not gate has two inputs R and
complement of present state Q(t)’ and
produces the next state Q(t+1) when enable is ‘1.’
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 -
D-Latch
This circuit addresses one
drawback of SR latch. That is, the
next state value can’t be predicted
when both inputs (S & R) are one.
D-latch is also known as data latch
(see diagram below).
State table of D-Latch is show below
D Q(t+1)
0 0
1 1
SR Flip Flop
SR flop-flop operates with only
positive clock transitions or
negative clock transitions.
Table below shows the stable
state of SR flip-flop
S R Q(t+1)
0 0 Q(t+1)
0 1 0
1 0 1
1 1 -
The following table shows the characteristics table of SR flip-flop
Present inputs Present Next state
state
S R Q(t) Q(t+1) Notes
0 0 0 0 State do not change
0 0 1 1
0 1 0 0 State changes to 0
0 1 1 0 when R is applied
1 0 0 1 State changes to 1
1 0 1 1 when S is applied
1 1 0 x Undetermined state
1 1 1 x
D-Flip-Flop
D flip-flop operates with only positive clock transitions or negative
clock transitions. The output of D flip flop is insensitive to the
changes in the input, D except for
active transition of the clock signal
(circuit diagram is shown below).
Below is the state table of D flip flop
D Q(t+1)
0 0
1 1
JK Flip-Flop
JK flip-flop is the modified version
of SR flip-flop. It operates only with
positive clock transitions or
negative clock transitions.
The state table for JK flip-flop is
shown below
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)’
The characteristic table of JK flip-flop is shown below
Present inputs Present state Next state
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
T Flip-Flop
T flip-flop is the simplified version of
JK flip-flop. It is obtained by
connecting the same input ‘T’ to
both inputs of JK flip-flop. It
operates with only positive clock
transitions or negative clock
transitions (see diagram).
State table for T flip-flop
T Q(t+1)
0 Q(t)
1 Q(t)’
Characteristic table for T flip-flop
Inputs Present state Next State
T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
