CHAPTER-5

Synchronous Sequential
Logic
Digital Design (with an introduction to the Verilog HDL) 6th Edition,
M. Morris Mano, Michael D. Ciletti

• Dr. Kalpana Settu

Assistant Professor
ECE, IIITDM Kancheepuram
 Outline

 Sequential Circuit
 Storage Elements: Latches
 Storage Elements: Flip-flops
 Analysis of Clocked Sequential Circuits
 HDL models (Skipped)
 State Reduction and Assignment
 Design Procedure

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 Sequential Circuits
 Sequential circuits employ storage elements or feedback path besides logic
gates. The outputs depend on both memory values (in the past) and present
values of inputs.

Feedback Path

 Inputs, present state

 Outputs, next state
 A sequential circuit is specified by a time sequence of inputs, outputs, and
internal states.

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 Synchronous and Asynchronous
 A synchronous sequential circuit: behavior defined at determined discrete instants
of time.
 A asynchronous sequential circuit: at any instant of time.
 Synchronization is achieved by a timing device called a clock generator, commonly
denoted by “clock” or “clk”.

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 Storage Elements
 An electronic device that can be used to store one bit of information.
 Two main types of storage elements
 latch
 flip-flop
 Latch: the storage element is controlled by signal levels (usually H or L), also
called level sensitive devices.
 Flip-flop: the storage element is controlled by a clock transition (i.e. LH or
HL), also called edge-sensitive devices.
Input Output Input Output
flip-
latch
flop
clk clk
LH
Level H
L
Edge

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 Storage Elements
 Trigger
 The state of a latch or flip-flop is switched by a change in the control input.
 Level triggered  latches
 Edge triggered  flip flops

Level triggered

Edge triggered

(leading-edge triggered)

Edge triggered

(trailing-edge triggered)

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 SR Latches with NOR Gates
 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates, and two inputs labeled S for set and R for reset.
 Q and Q’ are normally the complement of each other. Q = 1 and Q’ = 0, the latch is said
to be in the set state. Q = 0 and Q’ = 1, it is in the reset state.
 The SR latches constructed with two cross-coupled NOR gates are active-high.

 S=1, R=0  set state (Q will become 1)

 S=0, R=1  reset state (Q will become 0)

 When S=0 and R=0  keep the current

value

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 SR Latches with NOR Gates
0 0
1 1

0 0
1 0

1 0
0 0

1 0 1
0

1 0
0 0

 S=1, R=O  set state (Q will become to 1)

 S=O, R=1  reset state (Q will become to O)
0 0 0  When S=O and R=O  keep the current value
1
Not mutually complementary Forbidden!!!
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 SR Latch Timing Waveform
Assume initial value Qinit = 0
Q
S R Q
1 0 1
0 1 0
0 0 Hold

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 SR Latches with NAND Gates
 The SR latches constructed with two cross-coupled NAND gates are active-low
 S=1, R=O  reset state (Q will become to O)
 S=O, R=1  set state (Q will become to 1)
 S=1, R=1  unchanged

What is the difference between SR

latches with NOR gates and NAND
gates?
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 SR Latches with NAND Gates
1 1
0 0

1 1 1
0

0 1
1 1

0 1 0
1

0 1
1 1

 S=1, R=O  reset state (Q will become to 0)

S=O, R=1  set state (Q will become to 1)
1 1 1


0  When S=1 and R=1  keep the current value

Not mutually complementary Forbidden!!!

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 SR Latch with Control Input
 Add an additional control input to determine when the state of the latch can
be changed
 En = 0: S and R are disabled (no change at outputs)
 En = 1: S and R are active-high

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 D Latch (Transparent Latch)
 Eliminate the indeterminate state in the SR latches
 D latch has only two inputs: D (data) and En (control)
 Use the value of D to set the output value
 The D input goes directly to the S input and its complement is applied to the R
input
 D=1  S=1, R=0  Q=1

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D Latch Timing Waveform

Q
Assume initial value Qinit = 0

En

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 Graphic symbols for Latches

 You should know the operation in your mind when seeing the block diagrams of
latches.
 SR latch: (S,R) = (1,0) (0,1) (0,0)
 S’R’ latch: (S,R) = (0,1) (1,0) (1,1)
 In the case of a NAND gate latch, bubbles are added to the inputs to indicate that setting
and resetting occur with a logic-0 signal.
 D latch: En, D
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 Storage Elements: Flip-flops
 The state of a latch or flip-flop is switched by a change in the control input. This
momentary change is called a trigger, and the transition it causes is said to trigger the
flip-flop.

Level triggered

Edge triggered

(leading-edge
triggered)

Edge triggered

(trailing-edge
triggered)
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 Negative Edge-Triggered D Flip-flops

 Constructed with two D latches and an inverter

 The first latch (master) is enabled when CLK=1
 the data from the external D input are transferred to the master
 The second latch (slave) is enabled when CLK=0
 When the clock pulse returns to 0, the master is disabled and is isolated from the D input.
 At the same time, the slave is enabled and the value of Y is transferred to the output of the flip-flop
at Q.
 The circuit samples the D input and changes its output Q only at the negative-edge of the controlling
clock
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 Negative Edge-Triggered D Flip-flops
latch
latch

H
L
 Only the transition from high to low, the input D can be passed over the cascaded latches
 Negative edge-triggered
 How do you change it to positive edge-triggered?

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 Positive Edge-Triggered D Flip-flops
 An edge-triggered D flip-flop uses three SR
latches
 Two latches respond to the external D (data) and
Clk (clock) inputs.
 The third latch provides the outputs for the flip-
flop.
 when the input clock in the positive-edge-
triggered flip-flop makes a positive transition, the
value of D is transferred to Q.
 A negative transition of the clock (i.e., from 1 to 0)
does not affect the output, nor is the output
affected by changes in D when Clk is in the
steady logic-1 level or the logic-0 level.
 Hence, this type of flip-flop responds to the
transition from 0 to 1 and nothing else.
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D Flip-flop

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 Setup Time and Hold Time
• The timing of the response of a flip-flop to input data and to the clock must be
taken into consideration when one is using edge-triggered flip-flops.
• There is a minimum time called the setup time during which the D input must be
maintained at a constant value prior to the occurrence of the clock transition.
• Similarly, there is a minimum time called the hold time during which the D input
must not change after the application of the positive transition of the clock.
• The propagation delay time of the flip-flop is defined as the interval between the
trigger edge and the stabilization of the output to a new state.

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 DFF (D Flip-Flop) Symbol
 The dynamic indicator (> ) denotes the fact that the flip-flop responds to the
edge transition of the clock.
 A bubble o( ) outside the block adjacent to the dynamic indicator designates a
negative edge trigger.

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 Characteristic Table
 A characteristic table defines the logical properties of a flip-flop by describing its
operation in tabular form.
 The table defines the next state as a function of the inputs and the present state.
 Q(t) refers to the present state (i.e., the state present prior to the application of a clock edge).
Q(t + 1) is the next state one clock period later.
 Note that the clock edge input is not included in the characteristic table, but is implied to
occur between times t and t + 1.
 Q(t)  state of the flip-flop immediately before the clock edge
 Q(t + 1)  state that results from the clock transition
Characteristic Table Characteristic Equation

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 Other Flip-Flops
 JK and T flip-flops
 There are three operations that can be performed with a flip-flop:
• Set it to 1
• reset it to 0
• Complement its output
 With only a single input, the D flip-flop can set or reset the output,
depending on the value of the D input immediately before the clock
transition.
 Synchronized by a clock signal, the JK flip-flop has two inputs and
performs all three operations.
 The T (toggle) flip-flop is a complementing flip-flop.

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 JK Flip-Flops
 JK flip-flop function: The J input sets the flip-flop to 1, the K input resets it to 0, and
when both inputs are enabled, the output is complemented.

(1). (J=1，K=0)  D  JQ  K Q  1 Q  1 Q  Q  Q  1

(2). (J=0，K=1)  D  JQ  K Q  0  Q  0  Q  0  0  0
(3). (J=1，K=1)  D  JQ  K Q  1 Q  0  Q  Q
(4). (J=0，K=0)  D  JQ  K Q  0  Q  1 Q  Q , No change

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 Characteristic Table
JK Flip-Flop
Characteristic Table Graphic symbol

Characteristic Equation

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 T Flip-Flops
 T flip-flop: “toggle” flip-flop  complementing flip-flop
 Constructed with JK flip-flop when inputs J and K are tied
together
 When T = 0 (J = K = 0), a clock edge does not change the
output.
 When T = 1 (J = K = 1), a clock edge complements the output.

(3). (J=1，K=1)  D  JQ  K Q  1 Q  0  Q  Q

(4). (J=0，K=0)  D  JQ  K Q  0  Q  1 Q  Q

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 T Flip-Flops
 T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate

 D  T  Q  TQ  T Q
 When T = 0, D = Q  no change
 When T = 1, D = Q’  complement

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 Characteristic Table
T Flip-Flop
Assume initial value Qinit = 0
Q

Clk

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 DFF with Asynchronous Reset
 Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state
independently of the clock.
 The input that sets the flip-flop to 1 is called preset or direct set.
 The input that clears the flip-flop to 0 is called clear or direct reset.

1
1
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 DFF with Asynchronous Reset
 Asynchronous reset is used to force the flip-flop to reset to 0, independently of the
clock.

 Active high reset: a circuit is reset when R = “1”.

 Active low reset: a circuit is reset when R = “0”.

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 Analysis of Clocked Sequential Circuits
 Analysis describes what a given circuit will do under certain operating conditions.
 The behavior of a clocked sequential circuit is determined from the inputs, the
outputs, and the state of its flip-flops.
 The analysis of a sequential circuit consists of obtaining a table or a diagram for
the time sequence of inputs, outputs, and internal states.

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Analysis of Clocked Sequential Circuits
 The next state of a flip-flop is determined by
 Input values
 Current state of the FF
 Clock trigger

input value determines Q(t + 1)

Value @ D input
Current output Q(t)

next clock edge comes

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 State Equations (Transition Equations)

 The behavior of a clocked sequential circuit can be described algebraically by

means of state equations.
 A state equation (also called a transition equation) specifies the next state as a
function of the present state and inputs.
 A state equation is an algebraic expression that specifies the condition for a flip-
flop state transition.

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State Equations (Transition Equations)

D input of a flip-flop determines

the value of the next state

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 State Equations
 The left side of the equation, with (t + 1), denotes the next state of the flip-flop
one clock edge later.
 The right side of the equation is a Boolean expression that specifies the
present state and inputs.

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 State Table
 The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table (or transition table).
 The table consists of four sections labeled present state, input, next state, and output.
 The derivation of a state table requires listing all possible binary combinations of
present states and inputs.

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 State Table
• It is sometimes convenient to express the state table in a slightly different form
having only three sections: present state, next state, and output.

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 State Diagram
 The information available in a state table can be represented graphically in
the form of a state diagram.
Input / Output

State
Transition

State

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 State Diagram
x/y
(input / output) next
present
AB AB

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 State Table & State Diagram
 Summarized procedure:

 There is no difference between a state table and a state diagram.

 The state table is easier to derive from a given logic diagram and the state equation.
 The state diagram is the form more suitable for human interpretation of the circuit’s
operation.
 Easier for an HDL model in the form of gate-level description or in the form of a
behavior description
 Easier for the design of an automatic synthesis tool

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Flip-Flop Input Equations (Excitation Equations)
 The part of the circuit that generates the inputs to flip-flops is described
algebraically by a set of Boolean functions called flip-flop input equations.
 The flip-flop input equations can be used to obtain state equations.

D flip-flop with output A

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Output Equations
 External outputs are described
algebraically by a set of Boolean
functions called output equations.

 The Boolean expressions

associated with the input/output
equations specify the
combinational circuit part of the
sequential circuit

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 Analysis with DFF
 Input equation

The state equation

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Analysis with JK Flip-Flop

Characteristic equation for

JK flip-flop:

Write state equations

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 Analysis with JK Flip-Flop
 Characteristic equations of a JK flip-flop.

 Input equations of the circuit

 State equations of the circuit

Characteristic equation for
JK flip-flop:

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Analysis with JK Flip-Flop

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 Analysis with JK Flip-Flop
State Diagram of the Circuit

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Analysis with TFF
 Input equations

 Characteristic equations

 State equations of the circuit

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 Analysis with TFF

• As long as input x is
equal to 1, the circuit
State Table behaves as a binary
counter.
• Here, the output
depends on the present
state only and is
independent of the
input.
• The two values inside
each circle and
separated by a slash
are for the present state
and output.

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 Mealy Model and Moore Model
• A state machine is a sequential circuit having a limited (finite) number of
states occurring in a prescribed order.
FSM: finite state machine
Mealy FSM

Moore FSM

What is the difference?

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 Mealy Model and Moore Model

In the Mealy model

The output is a function of both the present state
and the input.
The outputs may change if the inputs change
during the clock cycle.
In the Moore model
The output is a function of only the present state.

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Mealy Machine

• Output y is a function of both input x and the

present state of A and B .
• The corresponding state diagram shows
both the input and output values, separated
by a slash along the directed lines between
the states.

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Moore Model

• The output is a function of the present

state only.
• The corresponding state diagram has
only inputs marked along the directed
lines.
• The outputs are the flip-flop states
marked inside the circles.

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Moore Model

• The output depends only on flip-flop

values, and that makes it a function of
the present state only.
• The input value in the state diagram is
labeled along the directed line, but the
output value is indicated inside the
circle together with the present state.

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 State Reduction and Assignment

 m flip-flops produce 2m states, a reduction in the number of states may

result in a reduction in the number of flip-flops.
 The reduction in the number of flip-flops in a sequential circuit is referred
to as the state-reduction problem.
 If identical input sequences are applied to two circuits and identical
outputs occur for all input sequences, then the two circuits are said to be
equivalent.
 State reduction is to find ways of reducing the number of states in a
sequential circuit without altering the input–output relationships.

56
 State Reduction
 As an example, consider the input sequence 01010110100 starting from the
initial state a.

57
 State Reduction

 “g” and “e” are

equivalent.
 Remove the
present state
“g”.
 Change next
state “g” to “e”.

“Two states are said to be equivalent if, for each

member of the set of inputs, they give exactly the
same output and send the circuit to the same state.”

58
State Reduction

 “d” and “f” are equivalent.

 Remove the present
state “f”. Change next
state “f” to “d”.

59
State Reduction
• This state diagram satisfies the
original input–output specifications
and will produce the required output
sequence for any given input
sequence.
• For the input sequence used
previously (01010110100), the same
output sequence results although the
state sequence is different.

60
 State Assignment
 In order to design a sequential circuit with physical components, it is necessary
to assign unique coded binary values to the states.
 Code the states to unique binary values.

61
 State Assignment
 Any binary number assignment is satisfactory as long as each state
is assigned a unique number.

62
 Design Procedure
 We have learned how to derive a state diagram from a sequential circuit:
(Sequential Circuit  State Equations  State Table  State Diagram)
 If the specification/state diagram is given, how do we design a sequential circuit?

63
 Design Procedure
• Suppose we wish to design a circuit that detects a sequence of three or more
consecutive 1’s in a string of bits coming through an input line (i.e., the input is a
serial bit stream ).
• It is derived by starting with state S0, the reset state.

• If the input is 0, the circuit stays in S0, but if the input is 1, it goes to
state S1 to indicate that a 1 was detected.
• If the next input is 1, the change is to state S2 to indicate the arrival
of two consecutive 1’s, but if the input is 0, the state goes back to S0.
• The third consecutive 1 sends the circuit to state S3. If more 1’s are
detected, the circuit stays in S3. Any 0 input sends the circuit back to
S0.
• In this way, the circuit stays in S3 as long as there are three or more
consecutive 1’s received.

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 Synthesis Using DFF
 Step 1: Assign states using binary codes
S0= 00, S1= 01, S2= 10, S3= 11

S0 S0 S1 0
S1 S0 S2 0
States A B S2 S0 S3 0
S0 0 0 S3 S0 S3 1
S1 0 1
S2 1 0
S3 1 1

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 Synthesis Using DFF
 Step 2: Make a binary-coded state table according to the state diagram

66
 Synthesis Using DFF
 Step 3: Find minterms of next states A(t+1), B(t+1) and output y (next states
A(t+1), B(t+1) are also DFF inputs).

67
 Synthesis Using DFF
 Step 4: Simplify the equations DA, DB and y, using K-map

68
 Synthesis Using DFF
 Step 5: Draw the circuit from equations.

69
 Excitation Tables
• The design of a sequential circuit with flip-flops other than the D type is complicated by
the fact that the input equations for the circuit must be derived indirectly from the state
table.
• During the design process, we usually know the transition from the present state to the
next state and wish to find the flip-flop input conditions that will cause the required
transition.
• For this reason, we need a table that lists the required inputs for a given change of state.
Such a table is called an excitation table .

+ +

70
 Synthesis Using JKFF
• Synthesize the sequential circuit specified by Table 5.13

71
Synthesis Using JKFF

72
Synthesis Using JKFF

73
 Synthesis Using TFF
• Designing a binary counter.
• An n -bit binary counter consists of n flip-flops that can count in binary from
0 to 2n - 1.

74
Synthesis Using TFF

75
Synthesis Using TFF

76
 The End

Reference:
1. Digital Design (with an introduction to the Verilog HDL) 6th Edition, M. Morris Mano,
Michael D. Ciletti

Note: The slides are supporting materials for the course “Digital Circuits” at IIITDM Kancheepuram.
Distribution without permission is prohibited.

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