Course Instructor: Kiran G DD&CO Lab 3rd semester
Solutions for the Experiments from 02 to 08.
Experiment-02:
Design a 4-bit full adder and simulate the same using basic gates.
Fig. Four-bit full adder
Verilog code for 4 bit full adder:
module adder_4bit(
input [3:0] a,
input [3:0] b,
input c0,
output [3:0] sum,
output carry_out );
wire c1, c2, c3;
full_adder f1(.a_fa(a[0]),.b_fa(b[0]),.c_in_fa(c0),.sum_fa(sum[0]),.carry_fa(c1));
//Instantiated
full_adder f2 (.a_fa(a[1]),.b_fa(b[1]),.c_in_fa(c1),.sum_fa(sum[1]),.carry_fa(c2));
full_adder f3(.a_fa(a[2]),.b_fa(b[2]),.c_in_fa(c2),.sum_fa(sum[2]),.carry_fa(c3));
full_adder f4(.a_fa(a[3]),.b_fa(b[3]),.c_in_fa(c3),.sum_fa(sum[3]),.carry_fa(carry_out));
endmodule
//code for full_adder
module full_adder(
input [3:0] a_fa, b_fa,
input c_in_fa,
output [3:0] sum_fa,
output carry_fa );
wire temp1, temp2, temp3;
half_adder h1 (.a_ha(a_fa),.b_ha(b_fa),.sum_ha(temp1),.carry_ha(temp3));
half_adder h2 (.a_ha(temp1),.b_ha(c_in_fa),.sum_ha(sum_fa),.carry_ha(temp2));
assign carry_fa = temp2 | temp3;
endmodule
//code for half_adder
module half_adder(
input [3:0] a_ha, b_ha,
output [3:0] sum_ha,
output carry_ha );
assign sum_ha = a_ha ^ b_ha;
assign carry_ha = a_ha & b_ha;
endmodule
Testbench for 4-bit binary adder:
module tb_binary;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;
// Outputs
wire [3:0] sum;
wire carry;
// Instantiate the DUT
adder_4bit dut (.a(a), .b(b), .c0(carry_in), .sum(sum), .carry_out(carry) );
initial
begin
a = 0; b = 0; carry_in=0;
#10;
a = 6; b = 9; carry_in=0;
#10;
a = 3; b = 3; carry_in=1;
#10;
a = 4; b = 5; carry_in=0;
#10;
a = 8; b = 2; carry_in=0;
#10;
a = 9; b = 9; carry_in=1;
#10;
end
endmodule
Experiment-03:
Design Verilog HDL to implement simple circuits using data flow, structural (gate
level), and behavioural model.
// Dataflow modelling for AND gate
module and_data_flow(
output wire Y,
input wire A,
input wire B );
assign Y = A & B;
endmodule
// Structural/Gate-level modelling for AND gate
module and1_gate_level(
output wire Y,
input wire A,
input wire B );
and g1 (Y, A, B);
endmodule
// Behavioural modelling for AND gate
module and1_behavioural(
output reg Y,
input wire A,
input wire B );
always @(A, B) //(A or B) or (*)
begin
if (A==1'b1 && B==1'b1)
begin
Y = 1'b1;
end
else
begin
Y = 1'b0;
end
end
endmodule
Experiment-04:
Design Verilog HDL to implement binary adder-subtractor – Half and full adder, Half
and full subtractor.
//half adder
module half_adder_dataflow(
output wire carry,
output wire sum,
input wire A,
input wire B );
assign sum = A^B;
assign carry = A&B;
endmodule
//full adder
module full_adder_structural(
output wire carry,
output wire sum,
input wire A,
input wire B,
input wire C_in);
// half adder model should be used
half_adder_dataflow g1(c1, s1, A, B);
half_adder_behavioural g2(c2, sum, s1, C_in);
xor g3(carry, c1, c2);
endmodule
module half_adder_dataflow(
output wire carry,
output wire sum,
input wire A,
input wire B );
assign sum = A^B;
assign carry = A&B;
endmodule
// half subtractor
module half_subtractor(
output wire borrow,
output wire difference,
input wire x,
input wire y);
assign {borrow, difference} = x - y;
endmodule
// full subtractor
module full_subtractor(
output wire borrow_out,
output wire difference,
input wire x,
input wire y,
input wire borrow_in);
wire b1, d1, b2;
half_subtractor g1(b1, d1, x, y);
half_subtractor g2(b2, difference, d1, borrow_in);
xor g3(borrow_out, b1, b2);
endmodule
module half_subtractor(
output wire borrow,
output wire difference,
input wire x,
input wire y);
assign {borrow, difference} = x - y;
endmodule
Experiment-05:
Design Verilog HDL to implement decimal/ BCD adder.
Fig. Block diagram of a decimal/BCD adder
Truth table: Binary to decimal/BCD converter.
Verilog code for Decimal/BCD addition:
module bcd_adder(a,b,carry_in,sum,carry);
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition
always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9)
begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Testbench for Decimal/BCD adder:
module tb_bcdadder;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;
// Outputs
wire [3:0] sum;
wire carry;
// Instantiate the DUT
bcd_adder dut (.a(a), .b(b), .carry_in(carry_in), .sum(sum), .carry(carry) );
initial begin // Apply Inputs
a = 0; b = 0; carry_in = 0; #10;
a = 6; b = 9; carry_in = 0; #10;
a = 3; b = 3; carry_in = 1; #10;
a = 4; b = 5; carry_in = 0; #10;
a = 8; b = 2; carry_in = 0; #10;
a = 9; b = 9; carry_in = 1; #10;
end endmodule
Experiment-06:
Design Verilog program to implement different types of multiplexer like 2:1 and 4:1
Fig. 4:1 Multiplexer (TT and expr’n) Fig. 4:1 Multiplexer (logical)
Verilog code for 4:1 mux using behavioural modelling:
Module 4_1_mux (i,s,y);
input [3:0]i;
input [1:0]s;
output reg y;
always @ (*)
begin
case (s)
2’b00: begin y=i[0]; end
2’b01: begin y=i[1]; end
2’b10: begin y=i[2]; end
2’b11: begin y=i[3]; end
Default: y=1’b0;
endcase
end
endmodule
Testbench for 4:1 mux:
module mux_tb();
reg [3:0]i;
reg [1:0]s;
wire y;
4_1_mux m1 (.i(i), .s(s), .y(y));
Initial
begin
i[3]=1'b0; i[2]=1'b0; i[1]=1'b0; i[0]=1'b1; s[1]=1'b0; s[0]=1'b0; #10;
i[3]=1'b0; i[2]=1'b0; i[1]=1'b1; i[0]=1'b0; s[1]=1'b0; s[0]=1'b1; #10;
i[3]=1'b0; i[2]=1'b1; i[1]=1'b0; i[0]=1'b0; s[1]=1'b1; s[0]=1'b0; #10;
i[3]=1'b1; i[2]=1'b1; i[1]=1'b0; i[0]=1'b0; s[1]=1'b1; s[0]=1'b1; #10;
end
endmodule
Experiment-07:
Design Verilog program to implement types of de-multiplexer such as 1:4 demux
Fig. 1:4 De-Multiplexer (LD and TT)
module 1_4_demux (y, s, din);
output reg [3:0] y;
input [1:0] s;
input din;
always @(*)
begin
case (s)
2'b00 : begin y[0] = din; end
2'b01 : begin y[1] = din; end
2'b10 : begin y[2] = din; end
2'b11 : begin y[3] = din; end
default: y[3:0]=4’b0000;
endcase
end
endmodule
Testbench for 1:4 demux:
module mux_tb();
reg din;
reg [1:0]s;
wire [3:0]y;
1_4_demux m1 (.din(din), .s(s), .y(y));
Initial
begin
din = 1’b1;
s = 2'b00; #10;
s = 2'b01; #10;
s = 2'b10; #10;
s = 2'b11; #10; end
endmodule
Experiment-08:
1. SR flip-flop:
Fig. Logical symbol for SR flip-flop
Fig. Truth table for SR flip-flop
Verilog code:
module srff_behav(s,r,clk, q, qbar);
input s,r,clk;
output reg q, qbar;
always@(posedge clk)
begin
if(s == 0 && r==1)
begin
q = 0;
qbar = 1;
end
else if(s==1 && r==0)
begin
q = 1;
qbar =0;
end
else if(s == 0 & r == 0)
begin
q <= q;
qbar <= qbar
end
end
endmodule
Test bench code:
module dff_tb;
reg S,R, CLK;
wire Q, QBAR;
srff_behav dut(.q(Q), .qbar(QBAR), .s(S), .r(R), .clk(CLK)); // instantiation by port name.
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
S= 1; R= 0; #100;
S= 0; R= 0; #100;
S= 0; R= 1; #100;
S= 0; R= 0; #100;
S= 1; R=1; #100;
end
endmodule
2. D flip-flop:
Fig. Truth table for D flip-flop
Fig. Logical symbol for D flip-flop
Verilog code:
module dff_behavioral(d,clk,clear,q,qbar);
input d, clk, reset;
output reg q, qbar;
always@(posedge clk)
begin
if(reset== 1)
q <= 0;
qbar <= 1;
else
q <= d;
qbar = !d;
end
endmodule
Test bench:
module dff_tb;
reg D, CLK,reset;
wire Q, QBAR;
dff_behavioral dut(.q(Q), .qbar(QBAR), .reset(reset), .d(D), .clk(CLK)); // instantiation by
port name.
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
reset=1; D <= 0; #100;
reset=0; D <= 1; #100;
D <= 0; #100;
D <= 1; #100;
end
endmodule
3. JK flip-flop:
Fig. Logical symbol for JK flip-flop
Fig. Truth table for JK flip-flop
Verilog code:
module jkff_behave(clk,j,knq,qbar);
input clk,j,k;
output reg q,qbar;
always@(posedge clk)
begin
if(k = =0 && j==1)
begin
q <= 0;
qbar <= 1;
end
else if(k==1 && j==0)
begin
q <= 1;
qbar <= 0;
end
else if(j = 0 & k = 0)
begin
q <= q;
qbar <= qbar;
end
else if(j = 1 & k = 1)
begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule
Test bench:
module jkff_tb ();
reg J,K, CLK;
wire Q, QBAR;
jkff_behave dut(.q(Q), .qbar(QBAR), .j(J), .k(K), .clk(CLK)); // instantiation by port name.
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
J= 1; K=1; #100;
end endmodule
